Single-fin CMOS transistors with embedded and cladded source/drain structures
Semiconductor devices and methods of forming the same include forming a dummy gate over a fin, which has a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer, to establish a channel region and source/drain regions. Source/drain extensions are grown on the lower semiconductor layer. Source/drain extensions are grown on the upper semiconductor layer. The dummy gate is replaced with a gate stack.
1. A method of forming a semiconductor device, comprising:
forming a dummy gate over a fin that comprises a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer to establish a channel region and source/drain regions;
growing source/drain extensions on the lower semiconductor layer;
growing source/drain extensions on the upper semiconductor layer, wherein one of the lower semiconductor layer and the upper semiconductor layer is embedded by the respective source/drain extensions and the other of the lower semiconductor layer and the upper semiconductor layer is cladded by the respective source/drain extensions; and
replacing the dummy gate with a gate stack.
2. The method of claim 1 , wherein the intermediate layer comprises a triple layer that includes a first outer layer of a first dielectric material, an inner layer of a second dielectric material, and a second outer layer of the first dielectric material.
3. The method of claim 2 , further comprising forming the fin by:
depositing a first layer of a first semiconductor material;
depositing a second layer of a second semiconductor material on the first layer;
depositing a third layer of the first semiconductor material on the second layer to form a stack;
etching fins from the stack to expose sidewalls of the second layer;
annealing sidewalls of the second layer to form first and second outer layers of a first preliminary dielectric material;
oxidizing an inner layer of the second layer to form an inner layer of the second dielectric material; and
nitridating the second layer to convert the sidewalls of the second layer to the first dielectric material.
4. The method of claim 3 , further comprising depositing a layer of activating material on sidewalls of the fin before annealing the sidewalls of the second layer.
5. The method of claim 1 , wherein growing the source/drain extensions on the lower semiconductor layer comprises cladding the lower semiconductor layer by growing material on sidewalls and a top surface of the lower semiconductor layer.
6. The method of claim 5 , wherein growing the source/drain extension on the lower semiconductor layer further comprises growing material on an underlying semiconductor layer to form an electrical contact.
7. The method of claim 5 , further comprising etching away the upper semiconductor layer and the intermediate layer in the source/drain regions before growing the source/drain extensions on the lower semiconductor layer.
8. The method of claim 1 , wherein growing the source/drain extensions on the upper semiconductor layer comprises cladding the upper semiconductor layer by growing material on sidewalls and a top surface of the upper semiconductor layer.
9. The method of claim 8 , further comprising forming a protective layer on the upper dielectric layer in the source/drain regions before growing the source/drain extensions on the lower semiconductor layer.
10. The method of claim 1 , wherein growing the source/drain extensions on the upper semiconductor layer is performed after growing the source/drain extensions on the lower semiconductor layer.
11. The method of claim 10 , further comprising forming a passivating insulator layer over the source/drain extensions on the lower semiconductor layer before growing the source/drain extensions on the upper semiconductor layer.
12. A method of forming a semiconductor device, comprising:
forming a dummy gate over a fin that comprises a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer to establish a channel region and source/drain regions;
performing an epitaxial growth process that grows source/drain extensions on the lower semiconductor layer, and also grows material on an underlying semiconductor substrate layer to form an electrical contact;
growing source/drain extensions on the upper semiconductor layer; and
replacing the dummy gate with a gate stack.
13. The method of claim 12 , wherein growing the source/drain extensions on the lower semiconductor layer comprises cladding the lower semiconductor layer by growing material on sidewalls and a top surface of the lower semiconductor layer.
14. The method of claim 13 , further comprising etching away the upper semiconductor layer and the intermediate layer in the source/drain regions before growing the source/drain extensions on the lower semiconductor layer.
15. The method of claim 12 , wherein growing the source/drain extensions on the upper semiconductor layer is performed after growing the source/drain extensions on the lower semiconductor layer.
16. A method of forming a semiconductor device, comprising:
forming a dummy gate over a fin that comprises a lower semiconductor layeran insulating intermediate layer, and an upper semiconductor layer to establish a channel region and source/drain regions;
growing source/drain extensions on the lower semiconductor layer;
etching away the upper semiconductor layer and the intermediate layer in the source/drain regions;
growing source/drain extensions on the upper semiconductor layer after etching away the upper semiconductor layer and the intermediate layer in the source/drain regions; and
replacing the dummy gate with a gate stack;
wherein growing the source/drain extensions on the upper semiconductor layer is performed after growing the source/drain extensions on the lower semiconductor layer.
17. The method of claim 16 , further comprising forming a passivating insulator layer over the source/drain extensions on the lower semiconductor layer before growing the source/drain extensions on the upper semiconductor layer.