IP Library Granted Patent US 11,720,479
Granted Patent B2
US 11,720,479 · App. 16/162,558 · Granted Aug 8, 2023

Real time analysis and control for a multiprocessor system

Inventors: Geoffrey N. Ellis (Santa Cruz, CA); John Mark Beardslee (Menlo Park, CA); Michael B. Doerr (Dripping Springs, TX); Ivan Aguayo (Austin, TX); Brian A. Dalio (Keller, TX)
Assignee: Coherent Logix, Incorporated
G06F11/3688G06F11/2242G06F11/3664G06F13/28G06F30/00G06F9/45504G06F30/34
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Quick Facts
Patent No.
US 11,720,479
App. No.
16/162,558
Granted
Aug 8, 2023
Kind
B2
Abstract

System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.

Claims (46)

1. A method, comprising:

executing application software using a first hardware resource of a multi-processor array, wherein the multi-processor array includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes a first subset of the plurality of processing elements;

in response to executing, using a second hardware resource of the multi-processor array, at least one probe command included in test software:

duplicating, by a particular processing element of the plurality of processing elements, a read operation on a portion of a data stream generated in the first hardware resource to generate a duplicate data block that includes a copy of the portion of the data stream;

filtering, by the particular processing element, the duplicate data block to generate a filtered data block;

writing, by the particular processing element, the filtered data block to an unused memory of the plurality of memories; and

generating, by the particular processing element, test results using the filtered data block; and

wherein the second hardware resource includes a second subset of the plurality of processing elements different than the first subset of the plurality of processing elements; and

verifying operation of the application software based on the test results.

2. The method of claim 1 , further comprising, generating the test software based on an analysis of the application software.

3. The method of claim 1 , wherein executing, using the second hardware resource, the at least one probe command includes sampling data generated during execution of the application software to generate data samples.

4. The method of claim 3 , wherein executing, using the second hardware resource, the at least one probe command includes processing the data samples to generate the test results.

5. The method of claim 3 , wherein executing, using the second hardware resource, the at least one probe command includes transmitting the test results to another computer system.

6. The method of claim 3 , wherein executing, using the second hardware resource, the at least one probe command includes sending one or more test data vectors to the first hardware resource, and wherein executing the application software using the first hardware resource includes operating on the one or more test data vectors.

7. The method of claim 3 , wherein executing the application software includes updating at least one register included in the first hardware resource, and wherein executing, using the second hardware resource, the at least one probe command includes polling the at least one register included in the first hardware resource.

8. A system, comprising:

a plurality of processing elements;

a plurality of memories; and

an interconnection network coupling the plurality of processing elements and the plurality of memories, wherein the interconnection network includes a plurality of communication elements arranged in an interspersed fashion with the plurality of processing elements;

wherein a first set of the plurality of processing elements is configured to execute application software; and

wherein a second set of the plurality of processing elements is configured to:

in response to an execution of at least one probe command included in test software:

duplicate a read operation on a portion of a data stream to generate a duplicate data block that includes a copy of the portion of the data stream, wherein the data stream is generated in the first set of the plurality of processing elements executing the application software;

filter the duplicated data block to generate a filtered data block;

write the filtered data block to an unused memory of the plurality of memories;

generate test results relating to the data stream using the filtered data block; and

verify operation of the application software based on the test results.

9. The system of claim 8 , wherein the test software is based on an analysis of the application software.

10. The system of claim 8 , wherein to execute the at least one probe command, the second set of the plurality of processing elements is further configured to sample data generated during execution of the application software to generate data samples.

11. The system of claim 10 , wherein to execute the at least one probe command, the second set of the plurality of processing elements is further configured to process the data samples to generate the test results.

12. The system of claim 10 , wherein to execute the at least one probe command, the second set of the plurality of processing elements is further configured to transmit the test results to another computer system.

13. The system of claim 10 , wherein to execute the at least one probe command, the second set of the plurality of processing elements is further configured to send one or more test data vectors to the first set of the plurality of processing elements, and wherein to execute the application software, the first set of the plurality of processing elements is further configured to operate on the one or more test data vectors.

14. A non-transitory computer-accessible storage medium having program instructions stored therein that, in response to execution by a multi-processor system, causes the multi-processor system to perform operations including:

executing application software using a first hardware resource of a multi-processor array, wherein the multi-processor array includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, and wherein the first hardware resource includes a first subset of the plurality of processing elements;

in response to executing, using a second hardware resource of the multi-processor array, at least one probe command included in test software:

duplicating, by a particular processing element of the plurality of processing elements, a read operation on a data stream generated in the first hardware resource to generate a duplicate data block that includes a copy of a portion of the data stream, wherein the second hardware resource includes a second subset of the plurality of processing elements different than the first subset of the plurality of processing elements;

filtering, by the particular processing element, the duplicate data block to generate a filtered data block;

writing, by the particular processing element, the filtered data block to an unused memory of the plurality of memories; and

generating test results using the filtered data block; and

verifying operation of the application software based on the test results.

15. The non-transitory computer-accessible storage medium of claim 14 , wherein the operations further include generating the test software based on an analysis of the application software.

16. The non-transitory computer-accessible storage medium of claim 14 , wherein executing, using the second hardware resource, the at least one probe command includes sampling data generated during execution of the application software to generate data samples.

17. The non-transitory computer-accessible storage medium of claim 16 , wherein executing, using the second hardware resource, the at least one probe command includes processing the data samples to generate the test results.

18. The non-transitory computer-accessible storage medium of claim 16 , wherein executing, using the second hardware resource, the at least one probe command includes transmitting the test results to another computer system.

19. The non-transitory computer-accessible storage medium of claim 16 , wherein executing, using the second hardware resource, the at least one probe command includes sending one or more test data vectors to the first hardware resource, and wherein executing the application software using the first hardware resource includes operating on the one or more test data vectors.

20. The non-transitory computer-accessible storage medium of claim 14 , wherein executing the application software includes updating at least one register included in the first hardware resource, and wherein executing, using the second hardware resource, the at least one probe command includes polling the at least one register included in the first hardware resource.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2025
From: PACIFIC CAP ACQUISITION FUND, LLC
To: HYPERX HOLDINGS LLC
Reel/Frame 072342/0090 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2025
From: COHERENT LOGIX, INC.
To: PACIFIC CAP ACQUISITION FUND, LLC
Reel/Frame 072370/0394 →
SECURITY INTEREST Recorded Apr 11, 2024
From: COHERENT LOGIX, INCORPORATED
To: ACP POST OAK CREDIT I LLC
Reel/Frame 067097/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2020
From: ELLIS, GEOFFREY N.; BEARDSLEE, JOHN MARK; DOERR, MICHAEL B.; AGUAYO, IVAN; DALIO, BRIAN A.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 052106/0796 →
Continuity (4)
Continuation 15276370 · Sep 26, 2016
Continuation 14074925 · Nov 8, 2013
Provisional Application 61724493 · Nov 9, 2012
Related Publication 20190050324A1 · Feb 14, 2019