Patent Assignment
Reel/Frame 072370/0394
Assignment of Assignor's Interest
Recorded: 2025-08-06
Pages: 44
Assignor
COHERENT LOGIX, INC.
Executed: 2024-08-30
Assignee
PACIFIC CAP ACQUISITION FUND, LLC
11620 WILSHIRE BLVD., LOS ANGELES, CALIFORNIA, 90025
Covered Properties
(259)
Execution of Hardware Description Language (Hdl) Programs
PCT:
PCT/US2005/022850 ↗
Programming a Multi-Processor System
PCT:
PCT/US2007/065268 ↗
Designing an Asic Based on Execution of a Software Program on a Processing System
PCT:
PCT/US2007/069481 ↗
Mobile Television Broadcast System
PCT:
PCT/US2008/069200 ↗
Transmission of Multimedia Streams to Mobile Devices with Cross Stream Association
PCT:
PCT/US2009/045487 ↗
Transmission of Multimedia Streams to Mobile Devices with Uncoded Transport Tunneling
PCT:
PCT/US2009/045650 ↗
Transmission of Multimedia Streams to Mobile Devices with Variable Training Information
PCT:
PCT/US2009/045763 ↗
Transmitting and Receiving Control Information for Use with Multimedia Streams
PCT:
PCT/US2009/046466 ↗
Parallel Execution of Trellis-Based Methods
PCT:
PCT/US2010/038944 ↗
Disabling Communication in a Multiprocessor System
PCT:
PCT/US2011/056438 ↗
Frequency Divider with Synchronous Range Extension Across Octave Boundaries
PCT:
PCT/US2012/022364 ↗
Three Dimensional Display Compute System
PCT:
PCT/US2012/051631 ↗
Processing System with Interspersed Processors Dma-Fifo
PCT:
PCT/US2013/029915 ↗
Processing System with Interspersed Processors with Multi-Layer Interconnect
PCT:
PCT/US2013/034125 ↗
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
PCT:
PCT/US2013/041942 ↗
A Distributed Architecture for Encoding and Delivering Video Content
PCT:
PCT/US2013/045256 ↗
Multiprocessor Programming Toolkit for Design Reuse
PCT:
PCT/US2013/063628 ↗
Processing System with Synchronization Instruction
PCT:
PCT/US2013/064366 ↗
Real Time Analysis and Control for a Multiprocessor System
PCT:
PCT/US2013/069075 ↗
Multiprocessor System with Improved Secondary Interconnection Network
PCT:
PCT/US2013/071307 ↗
Clock Distribution Network for Multi-Frequency Multi-Processor Systems
PCT:
PCT/US2013/075083 ↗
Automatic Selection of on-Chip Clock in Synchronous Digital Systems
PCT:
PCT/US2013/075112 ↗
Multi-Frequency Clock Skew Control for Inter-Chip Communication in Synchronous Digital Systems
PCT:
PCT/US2013/075132 ↗
Memory-Network Processor with Programmable Optimizations
PCT:
PCT/US2014/039345 ↗
Broadcast/Broadband Convergence Network
PCT:
PCT/US2014/050594 ↗
Parameterized Radio Waveform for Operating in Multiple Wireless Environments
PCT:
PCT/US2014/051681 ↗
Shared Spectrum Access for Broadcast and Bi-Directional, Packet-Switched Communications
PCT:
PCT/US2015/044524 ↗
Dna Alignment Using a Hierarchical Inverted Index Table
PCT:
PCT/US2016/058183 ↗
Memory Management and Path Sort Techniques in a Polar Code Successive Cancellation List Decoder
PCT:
PCT/US2016/063479 ↗
Processor Instructions to Accelerate Fec Encoding and Decoding
PCT:
PCT/US2016/068692 ↗
Scrambling Sequence Design for Multi-Mode Block Discrimination on Dci Blind Detection
PCT:
PCT/US2017/068972 ↗
Scrambling Sequence Design for Embedding Ue Id into Frozen Bits for Dci Blind Detection
PCT:
PCT/US2017/069014 ↗
Enhanced Polarization Weighting to Enable Scalability in Polar Code Bit Distribution
PCT:
PCT/US2018/031389 ↗
Scrambling Sequence Design for Multi-Mode Block Discrimination on Dci Blind Detection
PCT:
PCT/US2018/045355 ↗
Programming Flow for Multi-Processor System
PCT:
PCT/US2018/058700 ↗
Memory Network Processor
PCT:
PCT/US2018/058873 ↗
Low Latency Video Codec and Transmission with Parallel Processing
PCT:
PCT/US2018/065146 ↗
Any World View Generation
PCT:
PCT/US2019/052926 ↗
Shared Spectrum Access for Broadcast and Bi-Directional, Packet-Switched Communications
PCT:
PCT/US2019/057617 ↗
Home Power Distribution with Multiphase Bridging
PCT:
PCT/US2019/063660 ↗
A Comprehensive System Design to Address the Needs for Virtual Segmentation of the Coaxial Cable Plant
PCT:
PCT/US2020/016526 ↗
Flexible Diplexer with Dynamically Configurable Band-Split in Hybrid Fiber Coax Deployments
PCT:
PCT/US2021/030604 ↗
Modular Design Flow
PCT:
PCT/US2024/035617 ↗
Processing System with Interspersed Stall Propagating Processors and Communication Elements
Frequency Domain Equalization of Communication Signals
Execution of Hardware Description Language (Hdl) Programs
Programming a Multi-Processor System
Designing an Asic Based on Execution of a Software Program on a Processing System
Frequency Domain Equalization of Communication Signals
Processing System with Interspersed Processors and Communication Elements
Mobile Television Broadcast System
Transmission of Multimedia Streams to Mobile Devices with Cross Stream Association
Transmission of Multimedia Streams to Mobile Devices with Uncoded Transport Tunneling
Transmission of Multimedia Streams to Mobile Devices with Variable Training Information
Transmitting and Receiving Control Information for Use with Multimedia Streams
Processing System with Interspersed Processors Using Shared Memory of Communication Elements
Processing System with Interspersed Processors Using Selective Data Transfer Through Communication Elements
Parallel Execution of Trellis-Based Methods
Processing System with Interspersed Processors and Dynamic Pathway Creation
Designing an Asic Based on Execution of a Software Program on a Processing System
Detection of Low-Amplitude Echoes in a Received Communication Signal
Converting Portions of a Software Program Executing on a Processing System to Hardware Descriptions
Method and System for Disabling Communication Paths in a Multiprocessor Fabric by Setting Register Values to Disable the Communication Paths Specified by a Configuration
Stall Propagation in a Processing System with Interspersed Processors and Communicaton Elements
Frequency Divider with Synchronous Range Extension Across Octave Boundaries
Partial Hardening of a Software Program from a Software Implementation to a Hardware Implementation
Three Dimensional Display Compute System
Wireless Transmission of Multimedia Streams Which Uses Control Information to Associate Error Correction Coding with an Audiovisual Stream
Wireless Transport Framework with Variable Equalizer Training
Wireless transport framework with uncoded transport tunneling
Parallel Execution of Trellis-Based Methods
Processing System With Interspersed Processors DMA-FIFO
Processing System with Interspersed Processors with Multi-Layer Interconnect
Estimation of Low-Amplitude Echoes in a Received Communication Signal
Developing a Hardware Description Which Performs a Function by Partial Hardening of a Software Program on a Multi-Processor System
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Processing System with Interspersed Processors and Communication Elements Having Improved Wormhole Routing
Bit-Efficient Control Information for Use with Multimedia Streams
Distributed Architecture for Encoding and Delivering Video Content
Multiprocessor Programming Toolkit for Design Reuse
Processing System with Synchronization Instruction
Real Time Analysis and Control for a Multiprocessor System
Wireless Transport Framework with Variable Frequency Domain Training
Multiprocessor System with Improved Secondary Interconnection Network
Clock Distribution Network for Multi-Frequency Multi-Processor Systems
Automatic Selection of on-Chip Clock in Synchronous Digital Systems
Multi-Frequency Clock Skew Control for Inter-Chip Communication in Synchronous Digital Systems
Low-Amplitude Echo Estimation for a Received Communication Signal
Parallel Execution of Trellis-Based Methods Using Overlapping Sub-Sequences
Programming a Multi-Processor System
Memory-Network Processor with Programmable Optimizations
Processing System with Interspersed Processors and Communication Elements Having Improved Communication Routing
Broadcast/Broadband Convergence Network
Parameterized Radio Waveform for Operating in Multiple Wireless Environments
Multiprocessor Fabric Having Configurable Communication That Is Selectively Disabled for Secure Processing
Generating Control Information for use in Transmission with a Multimedia Stream to an Audiovisual Device
Multi-Frequency Clock Skew Control for Inter-Chip Communication in Synchronous Digital Systems
Parallel Processing of Overlapping Subsequences to Generate Soft Estimates
Wireless System with Variable Training Information Based on Device Type
Mechanisms for Low-Amplitude Echo Estimation
Shared Spectrum Access for Broadcast and Bi-Directional, Packet-Switched Communications
Three Dimensional Display System
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Programming a Multi-Processor System
Multiprocessor System with Improved Secondary Interconnection Network
Processing System with Synchronization Instruction
Secure Boot Sequence for Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric
Memory-Network Processor with Programmable Optimizations
Application:
15/211,134 →
Publication:
US 2016/0328231
Processing System With Interspersed Processors DMA-FIFO
Processing System With Interspersed Processors With Multi-Layer Interconnection
Clock Distribution Network for Multi-Frequency Multi-Processor Systems
Real Time Analysis and Control for a Multiprocessor System
DNA Alignment using a Hierarchical Inverted Index Table
Multimedia Streams Which Use Control Information to Associate Audiovisual Streams
Memory Management and Path Sort Techniques in a Polar Code Successive Cancellation List Decoder
Generating Control Information for use in Transmission with a Multimedia Stream to an Audiovisual Device
Processor Instructions to Accelerate FEC Encoding and Decoding
Multiprocessor System with Improved Secondary Interconnection Network
Processing System With Interspersed Processors With Multi-Layer Interconnection
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Multimedia Streams Which Use Control Information to Associate Audiovisual Streams
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Scrambling Sequence Design for Embedding UE ID into Frozen Bits for DCI Blind Detection
Multiprocessor Programming Toolkit for Design Reuse
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Programming a Multi-Processor System
Wireless Transport Framework with Uncoded Transport Tunneling
Path Sort Techniques in a Polar Code Successive Cancellation List Decoder
Enhanced Polarization Weighting to Enable Scalability in Polar Code Bit Distribution
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Processing System With Interspersed Processors With Multi-Layer Interconnection
Secure Boot Sequence for Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric
Broadcast/Broadband Convergence Network
Application:
16/018,907 →
Publication:
US 2018/0302798
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Real Time Analysis and Control for a Multiprocessor System
Programming Flow for Multi-Processor System
Memory Network Processor
Shared Spectrum Access for Broadcast and Bi-Directional, Packet-Switched Communications
Low Latency Video Codec and Transmission with Parallel Processing
Multiprocessor System with Improved Secondary Interconnection Network
Processing System With Interspersed Processors With Multi-Layer Interconnection
Generating Control Information for use in Transmission with a Multimedia Stream to an Audiovisual Device
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Control Information for a Wirelessly-Transmitted Data Stream
Scrambling Sequence Design for Embedding Receiver ID into Frozen Bits for Blind Detection
Memory-Network Processor with Programmable Optimizations
Audio Stagger Casting
Surround View Generation
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Home Power Distribution with Multiphase Bridging
Processing System with Interspersed Processors with Multi-Layer Interconnect
Enhanced Polarization Weighting to Enable Scalability in Polar Code Bit Distribution
Comprehensive System Design to Address the Needs for Virtual Segmentation of the Coaxial Cable Plant
Scrambling Sequence Design for Embedding Receiver ID into Frozen Bits for Blind Detection
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Wireless Transport Framework with Uncoded Transport Tunneling
Multiprocessor Programming Toolkit for Design Reuse
Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric
Application:
16/897,564 →
Publication:
US 2020/0302090
Processor Instructions to Accelerate FEC Encoding and Decoding
Multiprocessor System with Improved Secondary Interconnection Network
Memory Network Processor
Control Information for a Wirelessly-Transmitted Data Stream
Multimedia Streams Which Use Control Information to Associate Audiovisual Streams
Low Latency Video Codec and Transmission with Parallel Processing
Scrambling Sequence Design for Embedding Receiver ID into Frozen Bits for Blind Detection
Memory-Network Processor with Programmable Optimizations
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Flexible Diplexer with Dynamically Configurable Band-Split in Hybrid Fiber Coax Deployments
Application:
17/307,449 →
Publication:
US 2021/0351899
Processing System With Interspersed Processors DMA-FIFO
Broadcast/Broadband Convergence Network
Enhanced Polarization Weighting to Enable Scalability in Polar Code Bit Distribution
Multiprocessor Programming Toolkit for Design Reuse
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Home Power Distribution with Multiphase Bridging
Control Information for a Wirelessly-Transmitted Data Stream
Wireless Transport Framework with Uncoded Transport Tunneling
Shared Spectrum Access for Broadcast and Bi-Directional, Packet-Switched Communications
Comprehensive System Design to Address the Needs for Virtual Segmentation of the Coaxial Cable Plant
Low Latency Video Codec and Transmission with Parallel Processing
Memory Network Processor
Memory-Network Processor with Programmable Optimizations
DNA Alignment using a Hierarchical Inverted Index Table
Programming Flow for Multi-Processor System
Control Information for a Wirelessly-Transmitted Data Stream
Home Power Distribution with Multiphase Bridging
Wireless Transport Framework with Uncoded Transport Tunneling
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Real Time Analysis and Control for a Multiprocessor System
Application:
18/210,192 →
Publication:
US 2023/0359548
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Multiprocessor System with Improved Secondary Interconnection Network
Comprehensive System Design to Address the Needs for Virtual Segmentation of the Coaxial Cable Plant
Flexible Diplexer with Dynamically Configurable Band-Split in Hybrid Fiber Coax Deployments
Multiprocessor Programming Toolkit for Design Reuse
Parameterized Radio Waveform Techniques for Operating in Multiple Wireless Environments
Application:
18/651,959 →
Publication:
US 2025/0106651
Modular Design Flow
Application:
18/755,147 →
Publication:
US 2024/0427973
DNA Alignment using a Hierarchical Inverted Index Table
Application:
18/792,394 →
Publication:
US 2025/0174304
Comprehensive System Design to Address the Needs for Virtual Segmentation of the Coaxial Cable Plant
Application:
18/889,482 →
Publication:
US 2025/0158846
Programming Flow for Multi-Processor System
Application:
18/906,548 →
Publication:
US 2025/0181419
Wireless Transport Framework with Uncoded Transport Tunneling
Application:
18/913,227 →
Publication:
US 2025/0192804
Processing System with Interspersed Processors Dma-Fifo
Application:
18/985,560 →
Publication:
US 2025/0117271
Home Power Distribution with Multiphase Bridging
Application:
19/032,224 →
Publication:
US 2025/0168927
Control Information for a Wirelessly-Transmitted Data Stream
Application:
19/032,679 →
Publication:
US 2025/0184556
Flexible Diplexer with Dynamically Configurable Band-Split in Hybrid Fiber Coax Deployments
Application:
19/043,723 →
Publication:
US 2025/0184106
Multiprocessor System with Improved Secondary Interconnection Network
Application:
19/189,391 →
Publication:
US 2025/0252065
Shared Spectrum Access for Broadcast and Bi-Directional, Packet-Switched Communications
Application:
19/197,118 →
Publication:
US 2025/0287459
Mathematical matrix algorithm processor (MMAP)
Application:
60/391,734 →
Frequency domain equalization algorithm (FDEA)
Application:
60/396,819 →
Method and system for programming a multi-processor system
Application:
60/786,582 →
Electronic system design method from prototype to application specific integrated circuit
Application:
60/802,629 →
Robust Mobile TV Broadcast System
Application:
60/948,185 →
Robust mobile TV broadcast system
Application:
60/958,585 →
Enhanced mobile TV system
Application:
61/130,344 →
Enhanced mobile TV system with extensibility
Application:
61/131,165 →
Software Defined Methods for Extending the Applicability of a Massively Parallel Processor Architecture to Iterative Equalizer/Decoder
Application:
61/187,815 →
Software Defined Secure System
Application:
61/393,594 →
Frequency Divider with Synchronous Range Extension Across Octave Boundaries
Application:
61/437,126 →
3D Display Compute System
Application:
61/525,579 →
Rate Control for Video Compression
Application:
61/658,761 →
Multiprocessor Programming Toolkit for Design Reuse
Application:
61/722,850 →
Real Time Analysis and Control for a Multiprocessor System
Application:
61/724,493 →
Processing System with Interspersed Processors Dma-Fifo and Multi-Layer Interconnect
Application:
61/728,959 →
Processing System with Synchronization Instruction
Application:
61/734,190 →
Clock Distribution Network for Multi-Frequency Multi-Processor Systems
Application:
61/736,763 →
Secondary Interconnection Network Improvements
Application:
61/736,851 →
Memory-Network Processor with Programmable Optimizations
Application:
61/827,117 →
Broadcast/Broadband Convergence Network
Application:
61/864,631 →
Broadcast/Broadband Convergence Network
Application:
61/864,976 →
Parameterized Radio Waveform for Operating in Multiple Wireless Environments
Application:
61/867,434 →
Dynamic Configuration of a Flexible OFDM PHY Transport
Application:
62/034,583 →
Next Generation Broadcast Platform Preamble Signal Design and Signaling Protocol
Application:
62/041,478 →
Managed Coordination of Shared Spectrum Access from a Broadcast/Broadband Aware Wireless Base Station
Application:
62/041,534 →
System Discovery and Signaling
Application:
62/130,365 →
DNA Alignment
Application:
62/244,541 →
Memory Management in a Polar Code Successive Cancellation List Decoder
Application:
62/259,385 →
Memory Management and Path Sort Techniques in a Polar Code Successive Cancellation List Decoder
Application:
62/269,744 →
Processor Instructions to Accelerate FEC Encoding and Decoding
Application:
62/271,578 →
Memory Management and Path Sort Techniques in a Polar Code Successive Cancellation List Decoder
Application:
62/277,569 →
Early Termination with Polar Codes for eMBB DCI Blind Detection
Application:
62/442,225 →
Early Block Discrimination with Polar Codes to Further Accelerate DCI Blind Detection
Application:
62/455,448 →
Early Block Discrimination with Polar Codes to Further Accelerate DCI Blind Detection
Application:
62/501,493 →
Implementation Considerations for Polar Code Construction
Application:
62/503,172 →
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Application:
62/521,946 →
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Application:
62/544,616 →
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Application:
62/548,573 →
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Application:
62/556,598 →
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Application:
62/559,724 →
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Application:
62/566,922 →
Memory Network Processor
Application:
62/581,512 →
Programming Flow for Multi-Processor System
Application:
62/581,525 →
Propose a Rolling Slice Based Ip Hevc Encoder / Decoder
Application:
62/597,457 →
Low Latency Encoder with Parallel Processing
Application:
62/661,779 →
Surround View Generation
Application:
62/737,050 →
Home Power Distribution with Multiphase Bridging
Application:
62/772,706 →
Comprehensive System Design to Address the Needs for Virtual Segmentation of the Coaxial Cable Plant
Application:
62/801,026 →
Directional Birdwatching System
Application:
62/809,852 →
Flexible Diplexer with Dynamically Configurable Band-Split in Hybrid Fiber Coax Deployments
Application:
63/020,094 →
Modular Design Flow
Application:
63/510,330 →
Global & Local Clock Distribution Networks for Multiprocessor Systems
Application:
63/586,318 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Dec 23, 2022
From: COHERENT LOGIX, INCORPORATED
To: ACP POST OAK CREDIT I LLC
Reel/Frame 062214/0302 →
Security Interest
Jan 4, 2023
From: HYPERICE IP SUBCO, LLC
To: ACP POST OAK CREDIT I LLC
Reel/Frame 062269/0285 →
Security Interest
Apr 11, 2024
From: COHERENT LOGIX, INCORPORATED
To: ACP POST OAK CREDIT I LLC
Reel/Frame 067097/0363 →
Assignment of Assignor's Interest
Sep 20, 2024
From: SOLKA, MICHAEL B.; PURNELL, MICHAEL L.; TROCINO, MICHAEL R.; DOBBS, CARL S.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 068643/0246 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOBBS, CARL S.; TROCINO, MICHAEL R.; FAULKNER, KENNETH R.; SCHREPPEL, CHRISTOPHER L.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0708 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOBBS, CARL S.; MALIK, AFZAL M.; FAULKNER, KENNETH R.; SOLKA, MICHAEL B.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0832 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOBBS, CARL S.; TROCINO, MICHAEL R.; BINDLOSS, KEITH M.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0897 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOBBS, CARL S.; TROCINO, MICHAEL R.; SOLKA, MICHAEL B.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0955 →
Assignment of Assignor's Interest
Jul 16, 2025
From: LIM, STEPHEN E.; NGO, VIET N.; NICHOLSON, JEFFREY M.; BEARDSLEE, JOHN MARK
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071734/0016 →
Assignment of Assignor's Interest
Jul 16, 2025
From: BEARDSLEE, JOHN MARK; DOERR, MICHAEL B.; ENG, TOMMY K.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071731/0830 →
Assignment of Assignor's Interest
Jul 16, 2025
From: ENG, TOMMY K.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071731/0967 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOERR, MICHAEL B.; DOBBS, CARL S.; SOLKA, MICHAEL B.; TROCINO, MICHAEL R.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0142 →
Assignment of Assignor's Interest
Jul 16, 2025
From: SHELBY, KEVIN A.; NYSEN, PETER J.; DOERR, MICHAEL B.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071732/0410 →
Assignment of Assignor's Interest
Jul 16, 2025
From: MCGINN, COLLEEN J.; SHELBY, KEVIN A.; NYSEN, PETER J.; DOERR, MICHAEL B.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071732/0517 →
Assignment of Assignor's Interest
Jul 16, 2025
From: SHELBY, KEVIN A.; NYSEN, PETER J.; DOERR, MICHAEL B.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071732/0660 →
Assignment of Assignor's Interest
Jul 16, 2025
From: SHELBY, KEVIN A.; NYSEN, PETER J.; DOERR, MICHAEL B.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071732/0769 →
Assignment of Assignor's Interest
Jul 16, 2025
From: ENG, TOMMY KINMING
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071731/0683 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DRUMM, DAVID B.; GOLAB, JAMES P.; GARMANY, JAN D.; SHELBY, KEVIN L.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071732/0911 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOERR, MICHAEL B.; NYSEN, PETER J.; MCGINN, COLLEEN J.; SHELBY, KEVIN A.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071732/0263 →
Assignment of Assignor's Interest
Jul 16, 2025
From: CAVIN, MARK S.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0181 →
Assignment of Assignor's Interest
Jul 16, 2025
From: DOERR, MICHAEL B.; GARMANY, JAN D.; SOLKA, MICHAEL B.; HUNT, MARTIN A.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0282 →
Assignment of Assignor's Interest
Jul 16, 2025
From: BRUNS, MICHAEL W.; SOLKA, MICHAEL B.; DOBBS, CARL S.; HUNT, MARTIN A.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 071733/0636 →
Assignment of Assignor's Interest
Jul 17, 2025
From: BRUNS, MICHAEL W.; HUNT, MARTIN A.; SIDDAIAH, MANJUNATH H.; SIEVERS, JOHN C.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 072039/0219 →
Assignment of Assignor's Interest
Jul 17, 2025
From: BRUNS, MICHAEL W.; HUNT, MARTIN A.; SIDDAIAH, MANJUNATH H.
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 072039/0420 →
Assignment of Assignor's Interest
Jul 17, 2025
From: SHELBY, KEVIN A.; DOERR, MICHAEL B.; SOLKA, MICHAEL B.; YASHA, YAMA
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 072039/0425 →