Processing system with interspersed processors using shared memory of communication elements

1. A system, comprising:

a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and

a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine;

wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein the plurality of dynamically configurable communication elements are distinct from said plurality of processors;

wherein, for each of the processors, the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements;

wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of the plurality of said processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements; and

wherein, for each of said dynamically configurable communication elements, the first memory is shared among a plurality of the processors.

2. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory is shared among a plurality of neighboring processors.

3. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory is shared among four neighboring processors.

4. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory operates as at least a portion of a register file for its neighboring processors.

5. The system of claim 1 ,

wherein each of the processors is dynamically configurable to obtain data from the first memory of different ones of the dynamically configurable communication elements.

6. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory stores data that is directly accessible by a processor during execution of instructions.

7. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory stores data that is directly accessible by each of a plurality of neighboring processors during execution of instructions.

8. The system of claim 1 ,

wherein each of the processors is configured to obtain data from a first memory of any of a plurality of neighboring dynamically configurable communication elements.

9. The system of claim 1 ,

wherein a first processor is configured to obtain first data from a first memory of a first dynamically configurable communication element during a first time period, and wherein the first processor is configured to obtain second data from a first memory of a second dynamically configurable communication element during a second time period.

10. The system of claim 1 ,

wherein a first processor is configured to obtain a plurality of data values from a respective subset of the plurality of dynamically configurable communication elements simultaneously.

11. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory is configured to provide a plurality of data values to a respective subset of the plurality of processors simultaneously.

12. The system of claim 1 ,

wherein, for each of the dynamically configurable communication elements, the first memory is coupled to the plurality of communication ports via a plurality of access ports and includes a plurality of addressable locations; and

wherein, for each of the dynamically configurable communication elements, the routing engine is coupled to the plurality of communication ports and configured to route data between any of the plurality of communication ports.

13. The system of claim 1 , wherein each of the plurality of dynamically configurable communication elements further comprises a direct memory access engine coupled to the plurality of communication ports and configured to transfer data between the first memory and the plurality of communication ports.

14. A system, comprising:

a plurality of processors, each at least a subset of the plurality of processors comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and

a plurality of dynamically configurable communication elements, each of at least a subset of the plurality of dynamically configurable communication elements comprising a plurality of communication ports, a first memory, and a routing engine;

wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein the plurality of dynamically configurable communication elements are distinct from said plurality of processors;

wherein, for a first processor, the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements;

wherein, for a first dynamically configurable communication element, the plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements; and

wherein the memory of the first dynamically configurable communication element is shared among the first subset of the plurality of processors.

15. The system of claim 14 ,

wherein, the first subset of the plurality of processors are neighboring processors to the first dynamically configurable communication element.

16. The system of claim 14 ,

wherein each of the at least a subset of the plurality of processors is dynamically configurable to obtain data from memory of different ones of the dynamically configurable communication elements.

17. The system of claim 14 ,

wherein the first memory stores data that is directly accessible by a processor during execution of instructions.

18. The system of claim 14 ,

wherein a first processor is configured to obtain first data from the memory of the first dynamically configurable communication element during a first time period, and wherein the first processor is configured to obtain second data from a memory of a second dynamically configurable communication element during a second time period.

19. A method for operating a multiprocessor system, the method comprising:

executing at least one program on a plurality of processors, each processor comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports;

wherein said executing comprises:

at least a subset of the plurality of processors communicating with each other through a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a memory, and a routing engine, wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein the plurality of dynamically configurable communication elements are distinct from said plurality of processors;

configuring, for a first one of the dynamically configurable communication elements, a first subset of communication ports to couple to a first subset of the plurality of processors;

configuring, for the first one of the dynamically configurable communication elements, a second subset of communication ports to couple to a subset of the dynamically configurable communication elements; and

the first subset of the plurality of processors utilizing a memory of the first one of the dynamically configurable communication elements, wherein the memory of the first one of the dynamically configurable communication elements is shared among the first subset of the plurality of processors.

20. The method of claim 19 ,

wherein, the first subset of the plurality of processors are neighboring processors to the first dynamically configurable communication element.

21. The method of claim 19 ,

wherein each of the plurality of processors is dynamically configurable to obtain data from memory of different ones of the dynamically configurable communication elements.

22. The method of claim 19 ,

wherein the memory of the first one of the dynamically configurable communication elements stores data that is directly accessible by a processor during execution of instructions.

23. The method of claim 19 , wherein said executing comprises:

a first processor obtaining first data from the memory of the first dynamically configurable communication element during a first time period; and

the first processor obtaining second data from a memory of a second dynamically configurable communication element during a second time period.

24. A method of manufacturing an integrated circuit, the method comprising:

fabricating a unit comprising a processor and a dynamically configurable communication element;

wherein the processor comprises an arithmetic logic unit, an instruction processing unit, and a plurality of processor ports;

wherein the dynamically configurable communication element comprises a plurality of communication ports, a first memory, and a routing engine;

placing and interconnecting a plurality of the units on a substrate, wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein the plurality of dynamically configurable communication elements are distinct from said plurality of processors;

wherein, for each of the processors, the plurality of processor ports are configured for coupling to a first subset of the plurality of dynamically configurable communication elements;

wherein, for each of the dynamically configurable communication elements, the plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements;

wherein, for each of the dynamically configurable communication elements, the first memory is shared among a plurality of the processors.