Patent Assignment
Reel/Frame 062269/0285
Security Interest
Recorded: 2023-01-04
Pages: 12
Assignor
HYPERICE IP SUBCO, LLC
Executed: 2022-12-30
Assignee
ACP POST OAK CREDIT I LLC
777 POST OAK BLVD, SUITE 430, HOUSTON, TEXAS, 77056
Covered Properties
(60)
Laser Gyro Microprocessor Configuration and Control
Patent:
5,406,369 →
Application:
07/922,612 →
Processing System with Interspersed Stall Propagating Processors and Communication Elements
Execution of Hardware Description Language (Hdl) Programs
Programming a Multi-Processor System
Designing an Asic Based on Execution of a Software Program on a Processing System
Processing System with Interspersed Processors and Communication Elements
Processing System with Interspersed Processors Using Shared Memory of Communication Elements
Processing System with Interspersed Processors Using Selective Data Transfer Through Communication Elements
Parallel Execution of Trellis-Based Methods
Processing System with Interspersed Processors and Dynamic Pathway Creation
Designing an Asic Based on Execution of a Software Program on a Processing System
Converting Portions of a Software Program Executing on a Processing System to Hardware Descriptions
Method and System for Disabling Communication Paths in a Multiprocessor Fabric by Setting Register Values to Disable the Communication Paths Specified by a Configuration
Stall Propagation in a Processing System with Interspersed Processors and Communicaton Elements
Frequency Divider with Synchronous Range Extension Across Octave Boundaries
Partial Hardening of a Software Program from a Software Implementation to a Hardware Implementation
Three Dimensional Display Compute System
Parallel Execution of Trellis-Based Methods
Processing System With Interspersed Processors DMA-FIFO
Processing System with Interspersed Processors with Multi-Layer Interconnect
Developing a Hardware Description Which Performs a Function by Partial Hardening of a Software Program on a Multi-Processor System
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Processing System with Interspersed Processors and Communication Elements Having Improved Wormhole Routing
Multiprocessor Programming Toolkit for Design Reuse
Processing System with Synchronization Instruction
Real Time Analysis and Control for a Multiprocessor System
Multiprocessor System with Improved Secondary Interconnection Network
Clock Distribution Network for Multi-Frequency Multi-Processor Systems
Automatic Selection of on-Chip Clock in Synchronous Digital Systems
Multi-Frequency Clock Skew Control for Inter-Chip Communication in Synchronous Digital Systems
Parallel Execution of Trellis-Based Methods Using Overlapping Sub-Sequences
Programming a Multi-Processor System
Memory-Network Processor with Programmable Optimizations
Processing System with Interspersed Processors and Communication Elements Having Improved Communication Routing
Multiprocessor Fabric Having Configurable Communication That Is Selectively Disabled for Secure Processing
Multi-Frequency Clock Skew Control for Inter-Chip Communication in Synchronous Digital Systems
Parallel Processing of Overlapping Subsequences to Generate Soft Estimates
Three Dimensional Display System
Dynamic Reconfiguration of Applications on a Multi-Processor Embedded System
Programming a Multi-Processor System
Multiprocessor System with Improved Secondary Interconnection Network
Processing System with Synchronization Instruction
Secure Boot Sequence for Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric
Processing System With Interspersed Processors With Multi-Layer Interconnection
Clock Distribution Network for Multi-Frequency Multi-Processor Systems
Real Time Analysis and Control for a Multiprocessor System
Processor Instructions to Accelerate FEC Encoding and Decoding
Multiprocessor System with Improved Secondary Interconnection Network
Processing System With Interspersed Processors With Multi-Layer Interconnection
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Scrambling Sequence Design for Embedding UE ID into Frozen Bits for DCI Blind Detection
Multiprocessor Programming Toolkit for Design Reuse
Path Sort Techniques in a Polar Code Successive Cancellation List Decoder
Enhanced Polarization Weighting to Enable Scalability in Polar Code Bit Distribution
Processing System With Interspersed Processors With Multi-Layer Interconnection
Secure Boot Sequence for Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric
Scrambling Sequence Design for Multi-Mode Block Discrimination on DCI Blind Detection
Processing System With Interspersed Processors With Multi-Layer Interconnection
Scrambling Sequence Design for Embedding Receiver ID into Frozen Bits for Blind Detection
Enhanced Polarization Weighting to Enable Scalability in Polar Code Bit Distribution
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 14, 2012
From: DOERR, MICHAEL B.; GARMANY, JAN D.; SOLKA, MICHAEL B.; HUNT, MARTIN A.
To: COHERENT LOGIX INCORPORATED
Reel/Frame 028982/0814 →
Security Interest
Dec 23, 2022
From: COHERENT LOGIX, INCORPORATED
To: ACP POST OAK CREDIT I LLC
Reel/Frame 062214/0302 →
Security Interest
May 6, 2024
From: COHERENT LOGIX, INCORPORATED
To: PACIFIC CAP ACQUISITION FUND, LLC
Reel/Frame 067325/0476 →
Assignment of Assignor's Interest
Aug 6, 2025
From: COHERENT LOGIX, INC.
To: PACIFIC CAP ACQUISITION FUND, LLC
Reel/Frame 072370/0394 →
Assignment of Assignor's Interest
Aug 8, 2025
From: PACIFIC CAP ACQUISITION FUND, LLC
To: HYPERX HOLDINGS LLC
Reel/Frame 072342/0090 →