Partial hardening of a software program from a software implementation to a hardware implementation
View Patent ↗System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.
1. A method for developing a hardware description which performs a function, the method comprising:
storing a software program comprising program instructions which implement the function;
executing the software program on a processing system capable of parallel processing;
storing a first hardware description of at least a portion of the processing system, wherein the first hardware description specifies implementation of the at least a portion of the processing system;
generating a second hardware description that corresponds to the first hardware description, wherein the second hardware description comprises a first portion and a second portion, wherein the first portion specifies a dedicated hardware implementation of a first portion of the software program executing on a first portion of the processing system, and wherein the second portion specifies implementation of a second portion of the processing system;
wherein the second hardware description is configured to be implemented on an integrated circuit such that the integrated circuit implements the function.
2. The method of claim 1 ,
wherein said generating the first portion of the second hardware description comprises analyzing the first portion of the software program executing on the first portion of the processing system to determine an amount of hardware resources used.
3. The method of claim 1 ,
wherein said generating the first portion of the second hardware description comprises removing chip input/output.
4. The method of claim 1 ,
wherein the first portion of the first hardware description comprises programmable communication links with critical timing requirements;
wherein said generating the first portion of the second hardware description comprises replacing the programmable communication links with critical timing requirements with dedicated wires.
5. The method of claim 1 ,
wherein said generating the first portion of the second hardware description comprises removing unnecessary memory descriptions for unused memory.
6. The method of claim 1 ,
wherein said generating the first portion of the second hardware description comprises adjusting a memory size in the second hardware description.
7. The method of claim 1 ,
wherein said generating the first portion of the second hardware description comprises replacing one or more Random Access Memory (RAM) descriptions with one or more Read Only Memory (ROM) descriptions.
8. The method of claim 1 ,
wherein the first hardware description specifies a hardware description of the processing system having a first processor type;
wherein the second portion of the second hardware description is generated according to a second processor type.
9. A non-transitory, computer accessible memory medium storing program instructions for developing a hardware description which implements a function, wherein the program instructions are executable by a processer to:
execute a software program on a processing system capable of parallel processing, wherein the software program implements the function;
store a first hardware description of at least a portion of the processing system, wherein the first hardware description specifies implementation of the at least a portion of the processing system;
generate a second hardware description that corresponds to the first hardware description, wherein the second hardware description comprises a first portion and a second portion, wherein the first portion specifies a dedicated hardware implementation of a first portion of the software program executing on a first portion of the processing system, and wherein the second portion specifies implementation of a second portion of the processing system;
wherein the second hardware description is configured to be implemented on an integrated circuit such that the integrated circuit implements the function.
10. The non-transitory computer accessible memory medium of claim 9 ,
wherein said generating the first portion of the second hardware description comprises analyzing the first portion of the software program executing on the first portion of the processing system to determine an amount of hardware resources used.
11. The non-transitory computer accessible memory medium of claim 9 ,
wherein said generating the first portion of the second hardware description comprises removing chip input/output.
12. The non-transitory computer accessible memory medium of claim 9 ,
wherein the first portion of the first hardware description comprises programmable communication links with critical timing requirements;
wherein said generating the first portion of the second hardware description comprises replacing the programmable communication links with critical timing requirements with dedicated wires.
13. The non-transitory computer accessible memory medium of claim 9 ,
wherein said generating the first portion of the second hardware description comprises removing unnecessary memory descriptions for unused memory.
14. The non-transitory computer accessible memory medium of claim 9 ,
wherein said generating the first portion of the second hardware description comprises adjusting a memory size in the second hardware description.
15. The non-transitory computer accessible memory medium of claim 9 ,
wherein said generating the first portion of the second hardware description comprises replacing one or more Random Access Memory (RAM) descriptions with one or more Read Only Memory (ROM) descriptions.
16. The non-transitory computer accessible memory medium of claim 9 ,
wherein the first hardware description specifies a hardware description of the processing system having a first processor type;
wherein the second portion of the second hardware description is generated according to a second processor type.
17. A method for developing a hardware description which performs a function, the method comprising:
storing a software program comprising program instructions which implement the function;
executing the software program on a processing system capable of parallel processing;
storing a first hardware description of at least a portion of the processing system, wherein the first hardware description specifies implementation of the at least a portion of the processing system;
generating a second hardware description that corresponds to a first portion of the first hardware description, wherein the second hardware description specifies a dedicated hardware implementation of a first portion of the software program executing on a first portion of the processing system;
wherein the second hardware description and a second portion of the first hardware description are configured to be implemented on an integrated circuit such that the integrated circuit implements the function.
18. A non-transitory, computer accessible memory medium storing program instructions for developing a hardware description which implements a function, wherein the program instructions are executable by a processer to:
execute a software program on a processing system capable of parallel processing, wherein the software program implements the function;
store a first hardware description of at least a portion of the processing system, wherein the first hardware description specifies implementation of the at least a portion of the processing system;
generate a second hardware description that corresponds to a first portion of the first hardware description, wherein the second hardware description specifies a dedicated hardware implementation of a first portion of the software program executing on a first portion of the processing system;
wherein the second hardware description and a second portion of the first hardware description are configured to be implemented on an integrated circuit such that the integrated circuit implements the function.