Dynamic reconfiguration of applications on a multi-processor embedded system

1. An apparatus, comprising:

a first subset of a plurality of processors configured to execute a master task;

a second subset of the plurality of processors configured to execute a plurality of applications;

a plurality of memory circuits interspersed among the processors; and

a communication fabric interconnecting the plurality of processors and the plurality of memory circuits, wherein the communication fabric includes a plurality of buffer circuits interspersed among at least a subset of the plurality of processors, wherein the plurality of buffer circuits are configured to communicate data between the plurality of applications executing on the second subset of the plurality of processors via a first set of routes between a first subset of the plurality of buffer circuits;

wherein the first subset of the plurality of processors are configured, in response to executing the master task, to:

initiate storing one or more variable states associated with a first application of the plurality of applications;

initiate swapping the first application with a second application not included in the plurality of applications;

distribute instructions associated with the second application to different ones of the plurality of memory circuits via a second set of routes between a second subset of the plurality of buffer circuits;

execute the second application on the second subset of the plurality of processors; and

initiate restoring the first application by swapping the first application with a third application of the plurality of applications using the one or more variable states.

2. The apparatus of claim 1 , wherein to initiate the storing of the one or more variable states, the first subset of the plurality of processors are further configured to initiate transmitting the one or more variable states from one or more memory circuits of the plurality of memory circuits to a particular memory circuit external to a multi-processor system that includes the plurality of processors, the plurality of memory circuits, and the communication fabric.

3. The apparatus of claim 2 , wherein to initiate restoring the first application, the first subset of the plurality of processors are further configured to:

initiate retrieving the one or more variable states from the particular memory circuit;

initiate storing the one or more variable states in a subset of the plurality of memory circuits that will be used by the first application; and

initiate executing the first application, along with the second application, and the plurality of applications excluding the third application.

4. The apparatus of claim 1 , wherein to initiate swapping the first application, the first subset of the plurality of processors is further configured to initiate stopping the first application by halting a subset of the plurality of processors executing the first application.

5. The apparatus of claim 4 , wherein the first subset of the plurality of processors is further configured, in response to a determination that the subset of the plurality of processors have halted, to initiate performing one or more cleanup operations on resources associated with the first application.

6. The apparatus of claim 5 , wherein to initiate performing the one or more cleanup operations, the first subset of the plurality of processors is further configured to:

initiate resetting a subset of the plurality of memory circuits associated with the first application; and

initiate resetting one or more routes between the plurality of processors used by the first application.

7. A method, comprising:

loading a plurality of applications on a multi-processor system that includes a plurality of processors and a plurality of data memory routers interspersed among the plurality of processors, wherein the plurality of applications includes a first application;

executing the plurality of applications on the multi-processor system, wherein the plurality of applications execute together and communicate via a first set of routes established between a first subset of the plurality of data memory routers;

swapping the first application, while continuing executing remaining ones of the plurality of applications excluding the first application, with a second application not included in the plurality of applications;

wherein swapping the first application includes saving one or more variable states associated with the first application;

distributing instructions associated with the second application among different ones of the plurality of data memory routers via a second set of routes established between a second subset of the plurality of data memory routers;

executing the second application along with remaining ones of the plurality of applications; and

restoring the first application by swapping the first application with a third application of the plurality of applications using the one or more variable states.

8. The method of claim 7 , wherein saving the one or more variable states includes transmitting the one or more variable states from one or more memory circuits of the plurality of data memory routers to a particular memory circuit external to the multi-processor system.

9. The method of claim 8 , wherein restoring the first application includes:

retrieving the one or more variable states from the particular memory circuit;

storing the one or more variable states in a particular subset of the plurality of data memory routers that will be used by the first application; and

executing the first application, along with the second application, and the plurality of applications excluding the third application.

10. The method of claim 7 , wherein swapping the first application further includes stopping the first application by halting a subset of the plurality of processors executing the first application.

11. The method of claim 10 , further comprising, in response to determining the subset of the plurality of processors have halted, performing one or more cleanup operations on resources associated with the first application.

12. The method of claim 11 , wherein performing the one or more cleanup operations includes:

resetting a particular subset of the plurality of data memory routers associated with the first application; and

resetting one or more routes between the plurality of processors used by the first application.

13. The method of claim 7 , wherein swapping the first application further includes terminating communication between the first application and one or more of the plurality of applications.

14. A non-transitory computer-readable memory medium storing program instructions, wherein the program instructions are executable by a multi-processor system to perform operations including:

loading a plurality of applications on the multi-processor system that includes a plurality of processors and a plurality of data memory routers interspersed among the plurality of processors, wherein the plurality of applications includes a first application;

executing the plurality of applications on the multi-processor system, wherein the plurality of applications execute together and communicate via a first set of routes established between a first subset of the plurality of data memory routers;

swapping the first application, while continuing executing remaining ones of the plurality of applications excluding the first application, with a second application not included in the plurality of applications;

wherein swapping the first application includes saving one or more variable states associated with the first application;

distributing instructions associated with the second application among different ones of the plurality of data memory routers via a second set of routes established between a second subset of the plurality of data memory routers;

executing the second application along with remaining ones of the plurality of applications; and

restoring the first application by swapping the first application with a third application of the plurality of applications using the one or more variable states.

15. The non-transitory computer-readable memory medium of claim 14 , wherein saving the one or more variable states includes transmitting the one or more variable states from one or more data memory routers of the plurality of data memory routers to a particular memory circuit external to the multi-processor system.

16. The non-transitory computer-readable memory medium of claim 15 , wherein restoring the first application includes:

retrieving the one or more variable states from the particular memory circuit;

storing the one or more variable states in a subset of the plurality of data memory routers that will be used by the first application; and

executing the first application, along with the second application, and the plurality of applications excluding the third application.

17. The non-transitory computer-readable memory medium of claim 14 , wherein swapping the first application further includes stopping the first application by halting a subset of the plurality of processors executing the first application.

18. The non-transitory computer-readable memory medium of claim 17 , wherein the operations further include, in response to determining the subset of the plurality of processors have halted, performing one or more cleanup operations on resources associated with the first application.

19. The non-transitory computer-readable memory medium of claim 18 , wherein performing the one or more cleanup operations includes:

resetting a particular subset of the plurality of data memory routers associated with the first application; and

resetting one or more routes between the plurality of processors used by the first application.

20. The non-transitory computer-readable memory medium of claim 14 , wherein swapping the first application further includes terminating communication between the first application and one or more of the plurality of applications.