IP Library Granted Patent US 11,914,989
Granted Patent B2
US 11,914,989 · App. 17/513,336 · Granted Feb 27, 2024

Multiprocessor programming toolkit for design reuse

Inventors: Stephen E. Lim (Scotts Valley, CA); Viet N. Ngo (Austin, TX); Jeffrey M. Nicholson (Lakeville, MN); John Mark Beardslee (Menlo Park, CA); Teng-I Wang (Yorba Linda, CA); Zhong Qing Shang (Cupertino, CA); Michael Lyle Purnell (Scotts Valley, CA)
Assignee: Coherent Logix, Incorporated
G06F8/71G06F8/443G06F8/60
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Quick Facts
Patent No.
US 11,914,989
App. No.
17/513,336
Granted
Feb 27, 2024
Kind
B2
Abstract

Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell definitions that include: program instructions executable to perform a function and one or more language constructs. The software code may further instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, where the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports and the first and second cell instances are included in the third cell instance.

Claims (52)

1. A non-transitory computer-readable medium that stores software code deployable on a multiprocessor array (MPA), wherein the software code comprises a set of program instructions that:

specify one or more cell definitions that include:

program instructions executable to perform a function; and

one or more language constructs; and

instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, wherein the instantiation includes configuration of the one or more language constructs such that:

the first and second cell instances communicate via respective communication ports;

the first and second cell instances are included in the third cell instance;

a communication port of the first cell instance is coupled to a first communication port of the third cell instance; and

a communication port of the second cell instance is coupled to a second communication port of the third cell instance different from the first communication port of the third cell instance.

2. The non-transitory computer-readable medium of claim 1 , wherein the first cell instance includes one or more other cell instances.

3. The non-transitory computer-readable medium of claim 1 , wherein the first and third cell instances are instances of different cell definitions.

4. The non-transitory computer-readable medium of claim 1 , wherein the first and third cell instances are instances of the same cell definition but are configured to use different amounts of hardware resources of the MPA.

5. The non-transitory computer-readable medium of claim 1 , wherein the cell definition for the third cell instance specifies that it includes one or more cell instances.

6. The non-transitory computer-readable medium of claim 1 , wherein the one or more language constructs configure the third cell instance to include the first and second cell instances.

7. The non-transitory computer-readable medium of claim 1 , wherein the first and second cell instances are configured to communicate current hardware resource usage.

8. The non-transitory computer-readable medium of claim 1 , wherein the communication ports are mappable to dynamic routing circuitry of the MPA that routes communications between processing element of the MPA.

9. A method for configuring a multiprocessor array (MPA), wherein the MPA comprises hardware resources including a plurality of processors and a plurality of memories, the method comprising:

accessing software code, wherein the software code a set of program instructions that:

specify one or more cell definitions that include:

program instructions executable to perform a function; and

one or more language constructs; and

instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, wherein the instantiation includes configuration of the one or more language constructs such that:

the first and second cell instances communicate via respective communication ports;

the first and second cell instances are included in the third cell instance;

a communication port of the first cell instance is coupled to a first communication port of the third cell instance; and

a communication port of the second cell instance is coupled to a second communication port of the third cell instance different from the first communication port of the third cell instance; and

deploying the first, second, and third cell instances on the MPA.

10. The method of claim 9 , wherein the first cell instance includes one or more other cell instances.

11. The method of claim 9 , wherein the cell definition for the third cell instance specifies that it includes one or more cell instances.

12. The method of claim 9 , wherein the one or more language constructs configure the third cell instance to include the first and second cell instances.

13. The method of claim 9 , further comprising:

dynamically adjusting an amount of hardware resources of the MPA that is assigned to the first cell instance.

14. The method of claim 9 ,

wherein the first and second cell instances are configured to communicate current hardware resource usage.

15. A system, comprising:

one or more processors; and

one or more memories having program instructions stored thereon that are executable to deploy software code on a multiprocessor array (MPA), wherein the software code comprises a set of program instructions that:

specify one or more cell definitions that include:

program instructions executable to perform a function; and

one or more language constructs; and

instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, wherein the instantiation includes configuration of the one or more language constructs such that:

the first and second cell instances communicate via respective communication ports;

the first and second cell instances are included in the third cell instance;

a communication port of the first cell instance is coupled to a first communication port of the third cell instance; and

a communication port of the second cell instance is coupled to a second communication port of the third cell instance different from the first communication port of the third cell instance.

16. The system of claim 15 , wherein the first cell instance includes one or more other cell instances.

17. The system of claim 15 , wherein the one or more language constructs configure the third cell instance to include the first and second cell instances.

18. The system of claim 15 , wherein the deployment maps communication to dynamic routing circuitry of the MPA that is configured to routes communications between processing element of the MPA.

19. The system of claim 15 ,

wherein the cell definition for the third cell instance specifies that it includes one or more cell instances.

20. The system of claim 15 ,

wherein the first and second cell instances are configured to communicate current hardware resource usage.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2025
From: PACIFIC CAP ACQUISITION FUND, LLC
To: HYPERX HOLDINGS LLC
Reel/Frame 072342/0090 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2025
From: COHERENT LOGIX, INC.
To: PACIFIC CAP ACQUISITION FUND, LLC
Reel/Frame 072370/0394 →
SECURITY INTEREST Recorded Apr 11, 2024
From: COHERENT LOGIX, INCORPORATED
To: ACP POST OAK CREDIT I LLC
Reel/Frame 067097/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2021
From: LIM, STEPHEN E.; NGO, VIET N.; NICHOLSON, JEFFREY M.; BEARDSLEE, JOHN MARK; WANG, TENG-I; SHANG, ZHONG QING; PURNELL, MICHAEL LYLE
To: COHERENT LOGIX, INCORPORATED
Reel/Frame 057950/0946 →