MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
1 . An apparatus, comprising:
a bus controller coupled to at least one specified interface unit of a plurality of interface units, wherein each of the plurality of interface units is coupled to a respective processor of a plurality of processors and a respective router of a plurality of routers, wherein the plurality of routers form a primary interconnection network, wherein the plurality of interface units are coupled together to form a secondary interconnection network, wherein the bus controller is configured to:
send data to and receive data from the at least one specified interface unit;
arbitrate requests for access to the at least one specified interface unit; and
perform a comparison between messages received from each of two or more processors of the plurality of processors and perform a particular one of a plurality of actions based upon results of the comparison.
2 . The apparatus of claim 1 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match.
3 . The apparatus of claim 1 , further comprising:
an error handler unit.
4 . The apparatus of claim 3 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send a command to the error handler unit in response to a determination that the messages received from each of the two or more processors do not match.
5 . The apparatus of claim 4 , wherein the error handler unit is configured to report a tamper event in response to receiving the command from the bus controller.
6 . The apparatus of claim 4 , further comprising a plurality of Input/Output (I/O) circuits, wherein the error handler unit is configured to disable the I/O circuits in response to receiving the command from the bus controller.
7 . The apparatus of claim 4 , further comprising a plurality of fuses, wherein the error handler unit is configured to blow at least one fuse of the plurality of fuses in response to receiving the command from the bus controller.
8 . A method for communicating in a multiprocessor system, wherein the multiprocessor system comprises a plurality of processors and a plurality of data memory routers coupled together in an interspersed fashion, wherein the method is performed by a bus controller coupled to at least one specified interface unit of a plurality of interface units, wherein each of the plurality of interface units is coupled to a respective processor of a plurality of processors and a respective router of a plurality of routers, wherein the plurality of routers form a primary interconnection network, wherein the plurality of interface units are coupled together to form a secondary interconnection network, the method comprising:
sending data to and receiving data from the at least one specified interface unit;
arbitrating requests for access to the at least one specified interface unit; and
performing a comparison between messages received from each of two or more processors of the plurality of processors and perform a particular one of a plurality of actions based upon results of the comparison.
9 . The method of claim 8 , wherein performing the particular one of the plurality of actions comprises sending, by the bus controller, one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match.
10 . The method of claim 8 , wherein performing the particular one of the plurality of actions comprises, by the bus controller, sending a command to an error handler unit in response to a determination that the messages received from each of the two or more processors do not match.
11 . The method of claim 10 , further comprising:
by the error handler unit, reporting a tamper event in response to receiving the command from the bus controller.
12 . The method of claim 10 , further comprising:
by the error handler unit, disabling a plurality of Input/Output (I/O) circuits in response to receiving the command from the bus controller.
13 . The method of claim 10 , further comprising:
by the error handler unit, blowing at least one fuse of a plurality of fuses in response to receiving the command from the bus controller.
14 . An apparatus, comprising:
a bus controller coupled to at least a first interface unit and a second interface unit of a plurality of interface units, wherein each of the plurality of interface units is coupled to a respective processor of a plurality of processors and a respective router of a plurality of routers, wherein the plurality of routers form a primary interconnection network, wherein the plurality of interface units are coupled together to form a secondary interconnection network, wherein the bus controller is configured to:
send data to the first interface unit, and receive data from the second interface unit;
arbitrate requests for access to at least the first and second interface units;
perform a comparison between messages received from each of two or more processors of the plurality of processors; and
perform a particular one of a plurality of actions based upon results of the comparison.
15 . The apparatus of claim 14 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send one of the messages to the secondary interconnect network in response to a determination that the messages received from each of the two or more processors match.
16 . The apparatus of claim 14 , further comprising an error handler unit.
17 . The apparatus of claim 16 , wherein to perform the particular one of the plurality of actions, the bus controller is further configured to send a command to the error handler unit in response to a determination that the messages received from each of the two or more processors do not match.
18 . The apparatus of claim 17 , wherein the error handler unit is configured to report a tamper event in response to receiving the command from the bus controller.
19 . The apparatus of claim 17 , further comprising a plurality of Input/Output (I/O) circuits, wherein the error handler unit is configured to disable the I/O circuits in response to receiving the command from the bus controller.
20 . The apparatus of claim 17 , further comprising a plurality of fuses, wherein the error handler unit is configured to blow at least one fuse of the plurality of fuses in response to receiving the command from the bus controller.