Multiprocessor programming toolkit for design reuse
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may include first program instructions executable to perform a function. In some embodiments, the software code may also include one or more language constructs that are configurable to specify one or more one or more parameter inputs. In some embodiments, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In some embodiments, the hardware resources include multiple processors and may include multiple supporting memories.
1. A non-transitory computer-readable medium that stores software code deployable on a multiprocessor array (MPA), wherein the software code comprises:
a set of program instructions that include:
a first subset of program instructions that specify a first cell definition that includes:
program instructions executable to perform a first function; and
one or more first language constructs which are user configurable to specify one or more parameter inputs;
a second subset of program instructions that instantiate a first instance of the first cell definition; and
a third subset of program instructions that instantiate a second instance, wherein the second instance is an instance of the first cell definition or an instance of another cell definition specified by the first subset of program instructions;
wherein the set of program instructions specifies one or more operations to communicate current hardware resource usage by the first instance to the second instance in order to dynamically reallocate hardware resources of the MPA from the first instance for use by the second instance.
2. The non-transitory computer-readable medium of claim 1 , wherein the first and second instances are different instances of the first cell definition.
3. The non-transitory computer-readable medium of claim 1 , wherein the set of program instructions specifies one or more dynamic communication pathways between the first instance and the second instance that are routed and torn down during execution of the first instance.
4. The non-transitory computer-readable medium of claim 1 , wherein the one or more first language constructs are user configurable to specify one or more communication ports, wherein the one or more communication ports are user configurable to specify communication between the first instance and other software code deployed on the MPA.
5. The non-transitory computer-readable medium of claim 1 , wherein the reallocated hardware resources include one or more processing elements.
6. The non-transitory computer-readable medium of claim 1 , wherein the reallocated hardware resources include communication resources.
7. The non-transitory computer-readable medium of claim 6 , wherein the communications resources include one or more memory and routing elements of the MPA.
8. The non-transitory computer-readable medium of claim 1 , wherein the reallocated hardware resources include allocated memory space.
9. The non-transitory computer-readable medium of claim 1 , wherein the set of program instructions specifies that the first instance of the first cell definition is to be deployed using a portion of hardware resources assigned to a larger cell in which the first instance is included.
10. A method for configuring a multiprocessor array (MPA), wherein the MPA comprises hardware resources including a plurality of processors and a plurality of memories, the method comprising:
accessing software code, wherein the software code comprises:
a set of program instructions that include:
a first subset of program instructions that specify a first cell definition that includes:
program instructions executable to perform a first function; and
one or more first language constructs which are user configurable to specify one or more parameter inputs;
a second subset of program instructions that instantiate a first instance of the first cell definition; and
a third subset of program instructions that instantiate a second instance, wherein the second instance is an instance of the first cell definition or an instance of another of a cell definition specified by the first subset of program instructions;
wherein the set of program instructions specifies one or more operations to communicate current hardware resource usage by the first instance to the second instance in order to dynamically reallocate hardware resources of the MPA from the first instance for use by the second instance; and
deploying the first and second instances on the MPA.
11. The method of claim 10 , wherein the set of program instructions specifies one or more dynamic communication pathways between the first instance and the second instance, wherein the method further comprising dynamically routing and tearing down the one or more dynamic communication pathways in the MPA during execution of the first instance.
12. The method of claim 10 , wherein the reallocated hardware resources include one or more processing elements, one or more communication resources, or allocated memory space.
13. The method of claim 10 , further comprising:
deploying the first instance of the first cell definition using a portion of hardware resources assigned to a larger cell in which the first instance of the first cell definition is included.
14. A system, comprising:
one or more processors; and
one or more memories having program instructions stored thereon that are executable by the one or more processors to cause operations comprising:
deploying software code on a multiprocessor array (MPA), wherein the software code comprises a set of program instructions that include:
a first subset of program instructions that specify a first cell definition that includes:
program instructions executable to perform a first function; and
one or more first language constructs which are user configurable to specify one or more parameter inputs;
a second subset of program instructions that instantiate a first instance of the first cell definition; and
a third subset of program instructions that instantiate a second instance, wherein the second instance is an instance of the first cell definition or an instance of another cell definition specified by the first subset of program instructions;
wherein the set of program instructions specifies one or more operations to communicate current hardware resource usage by the first instance to the second instance and wherein the operations further comprise dynamically reallocate hardware resources of the MPA from the first instance for use by the second instance.
15. The system of claim 14 , wherein the operations further comprise:
dynamically routing one or more communication pathways for the first instance during execution of the first instance.
16. The system of claim 15 , wherein the dynamically routing includes setting up inputs and outputs between one or more memory and routing elements of the MPA.
17. The system of claim 14 , wherein the first and second instances are deployed on neighboring regions of the MPA.
18. The system of claim 14 , wherein the first and second instances are instances of the first cell definition.
19. The system of claim 14 , wherein the reallocated hardware resources include one or more processing elements.
20. The system of claim 14 , wherein the reallocated hardware resources include communication resources.