Real Time Analysis and Control for a Multiprocessor System

1 - 20 . (canceled)

21 . A method, comprising:

storing application software in a memory medium;

modifying the application software to include testing code and thereby obtain modified application software, wherein the testing code comprises an auxiliary send statement;

deploying the modified application software on first hardware resources of a multi-processor array (MPA), wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes a first subset of the plurality of processing elements;

receiving input data to stimulate a device-under-test (DUT);

generating, by the modified application software, first data in the DUT based on the input data;

executing, by the modified application software, a first send statement;

executing, by the modified application software, the auxiliary send statement to provide at least a subset of the first data to a pin at an edge of the MPA using at least one second hardware resource of the MPA; and

receiving the first data by a software defined test bench to analyze operation of the DUT.

22 . The method of claim 21 ,

wherein deploying the modified application software on the first hardware resources comprises deploying the testing code to execute on at least one of the first hardware resources using the at least one second hardware resource of the MPA.

23 . The method of claim 21 , further comprising:

modifying the application software to include at least one probe command, and wherein deploying the modified application software on the first hardware resources includes generating probe data in response to executing the at least one probe command.

24 . The method of claim 23 , wherein deploying the modified application software on the first hardware resources includes:

streaming, by a first direct memory access (DMA) engine of a plurality of DMA engines, data resulting from executing the application software and the probe data to a particular memory of the plurality of memories; and

streaming, by a second DMA engine of the plurality of DMA engines, the data resulting from executing the application software to a target location in the plurality of memories.

25 . The method of claim 24 , further comprising coordinating operation of the first and second DMA engines.

26 . The method of claim 21 ,

wherein the at least one second hardware resource of the MPA is different from the first hardware resources of the MPA.

27 . The method of claim 21 ,

wherein the software defined test bench analyzes operation of the DUT with negligible impact on DUT performance.

28 . A non-transitory computer-accessible storage medium having program instructions stored therein that are executable by a multi-processor array (MPA) to cause the MPA to:

store application software in the storage medium;

modify the application software to include testing code and thereby obtain modified application software, wherein the testing code comprises an auxiliary send statement;

deploy the modified application software on first hardware resources of the MPA, wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes a first subset of the plurality of processing elements;

receive input data to stimulate a device-under-test (DUT);

generate, by the modified application software, first data in the DUT based on the input data;

execute, by the modified application software, a first send statement;

execute, by the modified application software, the auxiliary send statement to provide at least a subset of the first data to a pin at an edge of the MPA using at least one second hardware resource of the MPA; and

receive the first data by a software defined test bench to analyze operation of the DUT.

29 . The non-transitory computer-accessible storage medium of claim 28 ,

wherein deploying the modified application software on the first hardware resources comprises deploying the testing code to execute on at least one of the first hardware resources using the at least one second hardware resource of the MPA.

30 . The non-transitory computer-accessible storage medium of claim 28 , wherein the program instructions are further executable to cause the MPA to:

modify the application software to include at least one probe command, and wherein deploying the modified application software on the first hardware resources includes generating probe data in response to executing the at least one probe command.

31 . The non-transitory computer-accessible storage medium of claim 30 , wherein deploying the modified application software on the first hardware resources includes:

streaming, by a first direct memory access (DMA) engine of a plurality of DMA engines, data resulting from executing the application software and the probe data to a particular memory of the plurality of memories; and

streaming, by a second DMA engine of the plurality of DMA engines, the data resulting from executing the application software to a target location in the plurality of memories.

32 . The non-transitory computer-accessible storage medium of claim 31 , wherein the program instructions are further executable to cause the MPA to:

coordinate operation of the first and second DMA engines.

33 . The non-transitory computer-accessible storage medium of claim 28 ,

wherein the at least one second hardware resource of the MPA is different from the first hardware resources of the MPA.

34 . The non-transitory computer-accessible storage medium of claim 28 ,

wherein the software defined test bench is configured to analyze operation of the DUT with negligible impact on DUT performance.

35 . A system, comprising:

a multi-processor array (MPA) comprising:

a plurality of memories configured to store instructions;

a plurality of processing elements; and

an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the plurality of processing elements is configured to receive the instructions and execute the instructions to cause the system to:

store application software in the storage medium;

modify the application software to include testing code and thereby obtain modified application software, wherein the testing code comprises an auxiliary send statement;

deploy the modified application software on first hardware resources of the MPA, wherein the MPA, wherein the first hardware resource includes a first subset of the plurality of processing elements;

receive input data to stimulate a device-under-test (DUT);

generate, by the modified application software, first data in the DUT based on the input data;

execute, by the modified application software, a first send statement;

execute, by the modified application software, the auxiliary send statement to provide at least a subset of the first data to a pin at an edge of the MPA using at least one second hardware resource of the MPA; and

receive the first data by a software defined test bench to analyze operation of the DUT.

36 . The system of claim 35 ,

wherein deploying the modified application software on the first hardware resources comprises deploying the testing code to execute on at least one of the first hardware resources using the at least one second hardware resource of the MPA.

37 . The system of claim 35 , wherein the instructions are further executable to cause the system to:

modify the application software to include at least one probe command, and wherein deploying the modified application software on the first hardware resources includes generating probe data in response to executing the at least one probe command.

38 . The system of claim 37 , wherein deploying the modified application software on the first hardware resources includes:

streaming, by a first direct memory access (DMA) engine of a plurality of DMA engines, data resulting from executing the application software and the probe data to a particular memory of the plurality of memories; and

streaming, by a second DMA engine of the plurality of DMA engines, the data resulting from executing the application software to a target location in the plurality of memories.

39 . The system of claim 38 , wherein the instructions are further executable to cause the system to:

coordinate operation of the first and second DMA engines.

40 . The system of claim 35 ,

wherein the at least one second hardware resource of the MPA is different from the first hardware resources of the MPA.

34 . The system of claim 28 ,

wherein the software defined test bench is configured to analyze operation of the DUT with negligible impact on DUT performance.