Array substrate, preparation method thereof and display panel

1. An array substrate comprising:

a first thin film transistor and a second thin film transistor over a substrate;

wherein the first thin film transistor comprises a first portion of a first insulating layer, the first insulating layer comprises a first recess corresponding to the second thin film transistor, and the second thin film transistor is located in the first recess;

wherein a thickness of a second portion of the first insulating layer, which is below a bottom of the first recess, is smaller than that of the first portion of the first insulating layer; and

wherein the first thin film transistor and the second thin film transistor are respectively a polysilicon thin film transistor and an oxide thin film transistor.

2. The array substrate according to claim 1 , wherein the second portion of the first insulating layer has a thickness of 0 μm.

3. The array substrate of claim 1 , further comprising:

a buffer layer disposed between a surface of the substrate and the first thin film transistor;

wherein the buffer layer comprises a second recess corresponding to the second thin film transistor, and the first recess and the second recess are stacked; and

wherein, a thickness of a portion of the buffer layer, which is below a bottom of the second recess, is smaller than that of a portion of the buffer layer which is below the first thin film transistor.

4. The array substrate of claim 1 ,

wherein the first thin film transistor is a top gate type thin film transistor, and the first thin film transistor comprises at least one of a first gate insulating layer or a first interlayer insulating layer; and

wherein the first insulating layer comprises the first gate insulating layer and/or the first interlayer insulating layer.

5. The array substrate of claim 4 , wherein

the first thin film transistor further comprises a first source electrode and a first drain electrode;

the second thin film transistor comprises a second gate electrode, a second source electrode, and a second drain electrode;

one of the following is disposed in a same layer as the first source electrode and the first drain electrode are disposed:

the second gate electrode, or

the second source electrode and the second drain electrode.

6. The array substrate of claim 1 , further comprising:

a lead region, the lead region having a through-hole which comprises a first sub-through-hole and a second sub-through-hole which are stacked, the second sub-through-hole being disposed adjacent to the substrate, and an aperture of the second sub-through-hole being smaller than an aperture of the first sub-through-hole; and

a conductive layer disposed at the second sub-through-hole.

7. The array substrate according to claim 6 , wherein

the first recess penetrates through same layer or layers as the first sub-through-hole penetrates through; and

the second recess penetrates through same layer or layers as the second sub-through-hole penetrates through.

8. The array substrate of claim 6 , wherein the substrate is a flexible substrate;

the array substrate further comprising a first organic layer disposed at the through-hole,

wherein the first organic layer is located on a side of the conductive layer, which is adjacent to the substrate, and the first organic layer covers a bottom surface and a side surface of the through-hole.

9. The array substrate according to claim 8 , further comprising:

a second organic layer,

wherein the second thin film transistor is disposed over the second organic layer; and

wherein the second organic layer is disposed in a same layer as the first organic layer is disposed.

10. The array substrate of claim 1 , wherein at least a portion of the second thin film transistor is disposed directly on the substrate.

11. A display panel comprising the array substrate of claim 1 .