Method of forming a top epitaxy source/drain structure for a vertical transistor
A metal is formed into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin. A patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer is formed on the metal and a topmost surface of the ILD material. A metal induced layer exchange anneal is then employed in which the metal and doped semiconductor material change places such that the doped semiconductor material is in direct contact with the topmost surface of the semiconductor fin. The exchanged doped semiconductor material, which provides a top source/drain structure of the vertical transistor, may have a different crystalline orientation than the topmost surface of the semiconductor fin.
1. A method of forming a semiconductor structure, the method comprising:
forming a metal into an opening that is located in an interlayer dielectric (ILD) material, wherein the ILD material laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and is directly on a physically exposed topmost surface of the semiconductor fin, and wherein the metal completely fills the opening and has a topmost surface that is coplanar with a topmost surface of the ILD material;
forming a patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer on the metal and the ILD material, wherein the membrane has a bottommost surface directly contacting the topmost surface of both the ILD material and the metal; and
performing an anneal at a temperature of less than 450° C. to cause metal induced layer exchange between the metal and the doped amorphous semiconductor material layer and to form an exchanged doped semiconductor material, wherein the exchanged doped semiconductor material is crystalline and is in direct physical contact with the topmost surface of the semiconductor fin.
2. The method of claim 1 , wherein the metal is composed of aluminum (Al), silver (Ag), gold (Au) or antimony (Sb).
3. The method of claim 1 , wherein the forming the metal comprises:
depositing, at a temperature below 450° C., a layer containing the metal in the opening and on the topmost surface of the ILD material; and
removing the layer containing the metal from the topmost surface of the ILD material.
4. The method of claim 1 , wherein the membrane is composed of a dielectric material and has a thickness that is below 10 nm.
5. The method of claim 1 , wherein the doped amorphous semiconductor material layer includes an n-type dopant and is composed of silicon, germanium, or a silicon germanium alloy.
6. The method of claim 1 , wherein the doped amorphous semiconductor material layer includes a p-type dopant and is composed of silicon, germanium, or a silicon germanium alloy.
7. The method of claim 1 , wherein the doped amorphous semiconductor material layer is formed utilizing a growth process that is performed at a temperature below 450° C.
8. The method of claim 1 , wherein the temperature of the anneal is from 200° C. to 400° C., and the anneal is performed in an inert ambient.
9. The method of claim 1 , wherein the anneal forms a layer of a metal/semiconductor mixture between the membrane and the exchanged metal.
10. The method of claim 1 , wherein the exchanged doped semiconductor material has a different crystalline orientation than the topmost surface of the semiconductor fin.
11. The method of claim 1 , further comprising removing the membrane and the exchanged metal after the anneal.
12. The method of claim 11 , further comprising recessing, after the removal of the membrane and the exchanged metal, the exchanged doped semiconductor material below the topmost surface of the ILD material.