Resistive random-access memory
Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.
1. A device, comprising:
a memory component formed on a substrate, wherein a first shape is formed on a first top surface of the memory component, wherein the first shape is a “V” shaped faceted edge having a plurality of pointed edges; and
a transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.
2. The device of claim 1 , further comprising:
a dielectric layer that covers the memory component and the transistor.
3. The device of claim 1 , further comprising:
a dielectric layer that covers the memory component and the transistor; and
a metal gate that covers the dielectric layer.
4. The device of claim 1 , further comprising:
a dielectric layer that covers the memory component and the transistor;
a metal gate that covers the dielectric layer; and
a first region composed of a semiconductor material selected from a group consisting of a silicon, an alloy, a germanium, a III-V compound semiconductor, and a II-IV semiconductor.
5. The device of claim 1 , further comprising:
a source region formed at a second portion of the memory component and the transistor, wherein the source region comprises a first material that electrically couples the memory component to the transistor.
6. A device, comprising:
a memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first top surface of the memory component; and
a transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component; and
a dielectric layer that covers the memory component and the transistor.
7. The device of claim 6 , wherein the first shape is a “V” shaped faceted edge having a plurality of pointed edges.
8. The device of claim 6 , wherein the first shape is a faceted edge having one or more pointed edges.
9. The device of claim 6 , further comprising:
a metal gate that covers the dielectric layer.
10. The device of claim 6 , further comprising:
a metal gate that covers the dielectric layer; and
a first region composed of a semiconductor material selected from a group consisting of a silicon, an alloy, a germanium, a III-V compound semiconductor, and a II-IV semiconductor.
11. The device of claim 6 , further comprising:
a source region formed at a second portion of the memory component and the transistor, wherein the source region comprises a first material that electrically couples the memory component to the transistor.
12. A device, comprising:
a memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first top surface of the memory component;
a transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component;
a dielectric layer that covers the memory component and the transistor; and
a metal gate that covers the dielectric layer.
13. The device of claim 12 , wherein the first shape is a “V” shaped faceted edge having a plurality of pointed edges.
14. The device of claim 12 , wherein the first shape is a faceted edge having one or more pointed edges.
15. The device of claim 12 , further comprising:
a first region composed of a semiconductor material selected from a group consisting of a silicon, an alloy, a germanium, a III-V compound semiconductor, and a II-IV semiconductor.
16. The device of claim 12 , further comprising:
a source region formed at a second portion of the memory component and the transistor, wherein the source region comprises a first material that electrically couples the memory component to the transistor.