Semiconductor package
A semiconductor package includes a support member having a first surface and a second surface, and having a through-hole, a first metal layer for shielding disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member, a connection member disposed on the first surface of the support member, and having a redistribution layer, a semiconductor chip disposed in the through-hole, an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member, a second metal layer for shielding disposed on the encapsulant, and connected to the first metal layer for shielding by a connecting trench via passing through the encapsulant, and a reinforcing via disposed in a region, overlapping the trench via for connection, of the support member, and connected to the first metal layer for shielding.
1. A semiconductor package, comprising:
a support member having a first surface and a second surface opposing each other, and having a through-hole;
a first metal layer disposed on an internal sidewall of the through-hole and the first surface and the second surface of the support member;
a connection member disposed on the first surface of the support member, and having a redistribution layer;
a semiconductor chip disposed in the through-hole, and having a connection pad connected to the redistribution layer;
an encapsulant sealing the semiconductor chip located in the through-hole, and covering the second surface of the support member;
a second metal layer disposed on the encapsulant, and connected to the first metal layer by a connecting trench via passing through the encapsulant; and
a reinforcing via disposed in a region, overlapping the connecting trench via, of the support member, and connected to the first metal layer.
2. The semiconductor package of claim 1 , wherein the reinforcing via includes a plurality of vias arranged along the region which overlaps the connecting trench via.
3. The semiconductor package of claim 1 , wherein the reinforcing via has a single trench structure extending along the region which overlaps the connecting trench via.
4. The semiconductor package of claim 3 , wherein the reinforcing via has a plurality of trench structures spaced apart at predetermined intervals along the region which overlaps the connecting trench via.
5. The semiconductor package of claim 1 , wherein the reinforcing via has a trapezoidal shape when viewed in a cross-section in a thickness direction of the support member.
6. The semiconductor package of claim 1 , wherein the reinforcing via is connected to a metal pattern located in the support member.
7. The semiconductor package of claim 1 , wherein the connecting trench via surrounds the through-hole in a plan view perpendicular to a thickness direction of the support member.
8. The semiconductor package of claim 1 , further comprising: a shielding via surrounding the connection member in a region, adjacent to an edge, of the connection member, and connected to the first metal layer.
9. The semiconductor package of claim 8 , wherein the shielding via is formed of a material the same as a material of the redistribution layer.
10. The semiconductor package of claim 1 , further comprising: a heat dissipating device disposed in a region, corresponding to the semiconductor chip, of the connection member.
11. The semiconductor package of claim 1 , wherein the reinforcing via includes a first via and a second via, located in a region adjacent to the region which overlaps the connecting trench via, and surrounding the through-hole.
12. A semiconductor package, comprising:
a support member having a first surface and a second surface opposing each other, and having a first through-hole and a second through-hole;
a first metal layer disposed on at least an internal sidewall of the second through-hole and the first surface and the second surface of the support member;
a connection member disposed on the first surface of the support member, and having a redistribution layer;
a semiconductor chip disposed in the first through-hole, and having a connection pad connected to the redistribution layer;
at least one passive component disposed in the second through-hole, and having a connection terminal connected to the redistribution layer;
an encapsulant sealing the semiconductor chip and the at least one passive component, and covering the second surface of the support member;
a second metal layer disposed on the encapsulant;
a connecting trench via passing through the encapsulant to connect the first metal layer to the second metal layer, and surrounding the first through-hole and the second through-hole in a plan view perpendicular to a thickness direction of the support member; and
a reinforcing via disposed in at least a portion of a region, overlapping the connecting trench via, of the support member, and connected to the first metal layer.
13. The semiconductor package of claim 12 , wherein the connecting trench via has a portion disposed along a region adjacent to an outer edge of the support member, and the reinforcing via has a portion disposed along a region adjacent to the outer edge of the support member.
14. The semiconductor package of claim 12 , further comprising: a shielding via surrounding the connection member in a region, adjacent to an edge, of the connection member, and having a via stack structure connected to the first metal layer.