Anti-fuse cell and chip having anti-fuse cells
View Patent ↗An anti-fuse cell includes a control device and an anti-fuse element is introduced. The control device includes a source node, a drain node and a gate node, wherein the gate node is electrically coupled to a word line and the drain node is electrically coupled to a bit line. The anti-fuse element includes a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer of the anti-fuse element is physically stacked upon a conductive layer and electrically connected to the source node of the control device, and first conductive layer is electrically coupled to a program line through a via. An anti-fuse cell having multiple anti-fuse elements and a chip having a plurality of anti-fuse cells are also introduced.
1. A chip, comprising a plurality of anti-fuse cells, each of the anti-fuse cells being coupled to a world line, a bit line and a program line, each of the anti-fuse cells comprising:
a control device, comprising a source node, a drain node and a gate node, wherein the gate node is electrically coupled to the word line and the drain node is electrically coupled to the bit line; and
an anti-fuse element, comprising a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer, the first conductive layer is coupled to the program line, and the second conductive layer is electrically coupled to the source node of the control device,
wherein the bit line is coupled to the drain node of the control device through a first level via on a first level conductive layer of the chip, the anti-fuse element is located at a third level conductive layer of the chip, and the second third level conductive layer is higher than the first level conductive layer.
2. The chip of claim 1 , wherein
the first conductive layer is coupled to the program line through a via, and
the second conductive layer is physically stacked upon a metal layer and the metal layer is electrically coupled to the source node of the control device.
3. The chip of claim 1 , wherein the first conductive layer and second conductive layer of the anti-fuse element are formed by a single conductive material or a plurality of stacked materials selected from a group consisting of Ti, TiN, Ni, Mo, Pt, Co, Ru, W, TaN, Cu and a combination thereof.
4. The chip of claim 1 , wherein the dielectric layer of the anti-fuse element is formed by a single dielectric material or a plurality of stacked dielectric materials selected from a group consisting of SiO2, SiOC, SiON, SiOCN, Si3N4, Carbon content oxide, Nitrogen content oxide, Carbon and Nitrogen content oxide, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), Y oxide (Y2O3), multiple metal content oxide, and a combination thereof.
5. The chip of claim 1 , each of the anti-fuse cells further comprising:
a first via, a second via, a first conductive line and a second conductive line, wherein
the first via and the first conductive line are coupled to the first conductive layer of the anti-fuse element,
the second via and the second conductive line are coupled to the second conductive layer of the anti-fuse element,
the first conductive line is coupled to the program line, and
the second conductive line is coupled to the source node of the control device.
6. The chip of claim 1 , wherein
the word line is parallel to the program line in a first routing direction, and
the bit line is substantially perpendicular to first routing direction.
7. The chip of claim 1 , wherein
the word line is located at a fourth level conductive layer, the fourth level conductive layer is located upon the first level conductive layer, and
the program line is located at a fifth level conductive layer, wherein the fifth level conductive layer is higher than the fourth level conductive layer.
8. The chip of claim 7 , wherein the plurality of the anti-fuse cell forms an array of anti-fuse cells, and the chip further comprising:
a plurality of landing pads, locating at a conductive layer that has lower level than the fifth level conductive layer, wherein the landing pads are configured to electrically coupled the program line to a driver circuit, the driver circuit is located outside the array of anti-fuse cells.
9. The chip of claim 8 , wherein the landing pads are located at a boundary of the array of anti-fuse cells.
10. The chip of claim 8 , the chip further comprising:
a plurality of non-anti-fuse cells, wherein the non-anti-fuse cells are located in a non-anti-fuse area, each of the anti-fuse elements of the anti-fuse cells are located in an anti-fuse area, and the non-anti-fuse area is separated from the anti-fuse area by at least one inter metal dielectric film.
11. The chip of claim 10 , wherein
each of the non-anti-fuse area and the anti-fuse area comprises a first etch stop dielectric layer and a second etch stop dielectric layer, and
the landing pads are located between the first etch stop dielectric layer and the second etch stop dielectric layer.
12. The chip of claim 11 , wherein the non-anti-fuse area further comprises:
an extra etch stop dielectric layer, located upon the first etch stop dielectric layer and the second etch stop dielectric layer.
13. An anti-fuse cell, being coupled to a world line, a bit line and a program line, the anti-fuse cell comprising:
a control device, comprising a source node, a drain node and a gate node, wherein the gate node is electrically coupled to the word line and the drain node is electrically coupled to the bit line; and
an anti-fuse element, comprising a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer,
wherein the second conductive layer of the anti-fuse element is physically stacked upon a conductive layer and electrically connected to the source node of the control device, and first conductive layer is electrically coupled to the program line through a via,
wherein the bit line is coupled to the drain node of the control device through a first level via on a first level conductive layer, the anti-fuse element is located at a second third level conductive layer, and the second third level conductive layer is higher than the first level conductive layer.
14. The anti-fuse cell of claim 13 , wherein the first conductive layer and second conductive layer of the anti-fuse element are formed by a single conductive material or a plurality of stacked materials selected from a group consisting of Ti, TiN, Ni, Mo, Pt, Co, Ru, W, TaN, Cu or a combination thereof.
15. The anti-fuse cell of claim 13 , wherein the dielectric layer of the anti-fuse element is formed by a single dielectric material or a plurality of stacked dielectric materials selected from a group consisting of SiO2, SiOC, SiON, SiOCN, Si3N4, Carbon content oxide, Nitrogen content oxide, Carbon and Nitrogen content oxide, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), Y oxide (Y2O3), multiple metal content oxide, or a combination thereof.
16. The anti-fuse cell of claim 13 , further comprising:
a first via, a second via, a first conductive line and a second conductive line, wherein
the first via and the first conductive line are coupled to the first conductive layer of the anti-fuse element,
the second via and the second conductive line are coupled to the second conductive layer of the anti-fuse element,
the first conductive line is coupled to the program line,
the second conductive line is coupled to the source node of the control device the word line is parallel to the program line in a first routing direction, and
the bit line is substantially perpendicular to first routing direction.
17. An anti-fuse cell, being coupled to a world line, a bit line and a program line, the anti-fuse cell comprising:
a control device, comprising a source node, a drain node and a gate node, wherein the gate node is electrically coupled to the word line and the drain node is electrically coupled to the bit line;
a first anti-fuse element, comprising a first conductive layer, a second conductive layer and a first dielectric layer, wherein the first dielectric layer is disposed between the first conductive layer and the second conductive layer; and
a second anti-fuse element, comprising a third conductive layer, a fourth conductive layer and a second dielectric layer, wherein the second dielectric layer is disposed between the third conductive layer and the fourth conductive layer,
wherein the first conductive layer and the third conductive layer are electrically coupled to the program line, and the second conductive layer and the fourth conductive layer are electrically coupled to the source node of the control device.
18. The anti-fuse cell of claim 17 , wherein the first anti-fuse element is adjacent and parallel to the second anti-fuse element.
19. The anti-fuse cell of claim 17 , wherein the first conductive layer and second conductive layer of the anti-fuse element are formed by a single conductive material or a plurality of stacked materials selected from a group consisting of Ti, TiN, Ni, Mo, Pt, Co, Ru, W, TaN, Cu or a combination thereof.
20. The anti-fuse cell of claim 17 , wherein the dielectric layer of the anti-fuse element is formed by a single dielectric material or a plurality of stacked dielectric materials selected from a group consisting of SiO2, SiOC, SiON, SiOCN, Si3N4, Carbon content oxide, Nitrogen content oxide, Carbon and Nitrogen content oxide, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), Y oxide (Y2O3), multiple metal content oxide, or a combination thereof.