Low power chip-to-chip bidirectional communications
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
1. A method comprising:
obtaining a set of forward-channel bits at a transmitter;
generating a plurality of symbols of a codeword based on a set of weights determined from the obtained set of forward-channel bits, the plurality of symbols of the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a corresponding weight of the set of weights applied to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors;
transmitting each symbol of the codeword as a signal over a respective wire of a multi-wire bus to a receiver; and
obtaining, at a common-mode multi-input comparator (MIC) in the transmitter via the multi-wire bus, symbols of a common-mode codeword formed using a common-mode sub-channel vector that is mutually orthogonal to the plurality of sub-channel vectors, the common-mode sub-channel vector weighted by a reverse-channel bit of a sequence of reverse-channel bits, the common-mode MIC generating an output corresponding to the reverse-channel bit of the sequence of reverse-channel bits.
2. The method of claim 1 , wherein a forward-channel bit of the set of forward-channel bits is transmitted using the common-mode sub-channel vector.
3. The method of claim 2 , wherein the forward-channel bit transmitted using the common-mode sub-channel vector is transmitted in a time interval when the sequence of reverse-channel bits is not being received.
4. The method of claim 1 , wherein the symbols of the common-mode codeword are received at a rate that is less than a symbol transmission rate of the plurality of symbols of the codeword.
5. The method of claim 4 , wherein the rate of the symbols of the common-mode codeword is 256 times slower than the symbol transmission rate of the plurality of symbols of the codeword.
6. The method of claim 1 , wherein the sequence of reverse-channel bits is formed using a serializer.
7. The method of claim 1 , wherein the sequence of reverse-channel bits comprises bits selected from the group consisting of: command bits, error information bits, and management information bits.
8. The method of claim 1 , wherein the plurality of sub-channel vectors and the common-mode sub-channel vector form an orthogonal matrix represented by M:
M
=
1
1
1
1
1
1
1
-
1
0
0
0
0
1
/
2
1
/
2
-
1
0
0
0
0
0
0
1
-
1
0
0
0
0
1
/
2
1
/
2
-
1
1
/
3
1
/
3
1
/
3
-
1
/
3
-
1
/
3
-
1
/
3
.
9. The method of claim 1 , wherein the common-mode MIC generates the reverse-channel bit by detecting a baseline voltage of the wires of the multi-wire bus.
10. The method of claim 1 , wherein the common-mode codeword is transmitted by sourcing or sinking current into the wires of the multi-wire bus.
11. An apparatus comprising:
an encoder configured to obtain a set of forward-channel bits at a transmitter, and to responsively generate a plurality of symbols of a codeword based on a set of weights determined from the set of forward-channel bits, the plurality of symbols of the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a corresponding weight of the set of weights applied to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors;
a plurality of line drivers, each line driver configured to transmit a respective symbol of the plurality of symbols of the codeword as a signal over a respective wire of a multi-wire bus to a receiver; and
a common-mode multi-input comparator (MIC) in the transmitter configured to receive, via the multi-wire bus, symbols of a common-mode codeword formed using a common-mode sub-channel vector that is mutually orthogonal to the plurality of sub-channel vectors, the common-mode sub-channel vector weighted by a reverse-channel bit of a sequence of reverse-channel bits, the common-mode MIC generating an output corresponding to a reverse-channel bit of the sequence of reverse-channel bits.
12. The apparatus of claim 11 , wherein the encoder is configured to generate a sub-channel constituent codeword of the plurality of sub-channel constituent codewords by weighting the common-mode sub-channel vector according to a forward-channel bit in the set of forward-channel bits.
13. The apparatus of claim 11 , wherein the encoder is configured to generate the sub-channel constituent codeword by weighting the common-mode sub-channel vector in a time interval when the symbols of the common-mode codeword are not being received.
14. The apparatus of claim 11 , wherein the common-mode MIC is configured to receive the symbols of the common-mode codeword at a rate that is less than a symbol transmission rate of the plurality of symbols of the codeword.
15. The apparatus of claim 14 , wherein the rate of the symbols of the common-mode codeword is 256 times slower than the symbol transmission rate of the received symbols.
16. The apparatus of claim 11 , wherein the sequence of reverse-channel bits is obtained from a serializer.
17. The apparatus of claim 11 , wherein the sequence of reverse-channel bits comprises bits selected from the group consisting of: command bits, error information bits, and management information bits.
18. The apparatus of claim 11 , wherein the common-mode MIC is configured to generate the reverse-channel bit by detecting a baseline voltage of the wires of the multi-wire bus.
19. The apparatus of claim 11 , further comprising a plurality of switched-current sources configured to sink or supply current to the wires of the multi-wire bus to transmit the common-mode codeword.
20. The apparatus of claim 11 , wherein the plurality of sub-channel vectors and the common-mode sub-channel vector form an orthogonal matrix represented by M:
M
=
1
1
1
1
1
1
1
-
1
0
0
0
0
1
/
2
1
/
2
-
1
0
0
0
0
0
0
1
-
1
0
0
0
0
1
/
2
1
/
2
-
1
1
/
3
1
/
3
1
/
3
-
1
/
3
-
1
/
3
-
1
/
3
.