IP Library › Granted Patent US 10,825,820
Granted Patent B2
US 10,825,820 · App. 16/174,189 · Granted Nov 3, 2020

Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit

Inventors: Johannes Mueller (Dresden, DE); Patrick Polakowski (Dresden, DE); Maximilian Drescher (Dresden, DE); Stefan Riedel (Dresden, DE)
Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V
H01L27/10894H01L27/10808H01L27/10826H01L27/10855H01L27/10879H01L27/1159H01L29/1087H01L29/40111H01L29/516H01L29/6684H01L29/78391H01L29/78
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Quick Facts
Patent No.
US 10,825,820
App. No.
16/174,189
Granted
Nov 3, 2020
Kind
B2
Abstract

The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Claims (42)

1. A microelectronic circuit, comprising:

a substrate,

a transistor,

a memory transistor comprising at least one capacitor, and

source contacts, bulk contacts and drain contacts for the transistor and the memory transistor,

wherein the transistor comprises at least one insulating layer and at least one metal layer,

wherein the memory transistor comprises at least one insulating layer and at least one metal layer,

wherein the insulating layer of the transistor and the insulating layer of the memory transistor are produced in a common step,

wherein the metal layer of the transistor and the metal layer of the memory transistor are produced in a common step,

wherein the metal layer of the memory transistor and the insulating layer of the memory transistor are parts of a MOS capacitor,

wherein a gate contact of the transistor is connected to the metal layer of the transistor, and

wherein a gate contact of the memory transistor is connected to a metal layer of the capacitor of the memory transistor.

2. The microelectronic circuit of claim 1 , manufactured using a method comprising:

providing the substrate,

producing a source contact, a bulk contact and a drain contact each for the transistor and for the memory transistor,

producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,

producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,

producing at least one capacitor as part of the memory transistor,

producing a gate contact connected to the metal layer of the transistor, and

producing the gate contact connected to a metal layer of the capacitor of the memory transistor.

3. A microelectronic circuit, comprising:

a substrate,

a transistor,

a memory transistor comprising at least one capacitor, and

source contacts, bulk contacts and drain contacts for the transistor and the memory transistor,

wherein the transistor comprises at least one insulating layer and at least one metal layer,

wherein the memory transistor comprises at least one insulating layer and at least one metal layer,

wherein the insulating layer of the transistor and the insulating layer of the memory transistor are produced in a common step,

wherein the metal layer of the transistor and the metal layer of the memory transistor are produced in a common step,

wherein a gate contact of the transistor is connected to the metal layer of the transistor, and

wherein a gate contact of the memory transistor is connected to a metal layer of the capacitor of the memory transistor,

wherein the layers of the memory transistor and the layers of the transistor are in a dielectric carrier, and

wherein a further metal layer is on the insulating layer and below a lower metal layer of the memory transistor, and wherein an intermediate conductive path is between the lower metal layer and the further metal layer in the dielectric carrier.

4. The microelectronic circuit of claim 3 ,

manufactured using a method comprising:

providing the substrate,

producing a source contact, a bulk contact and a drain contact each for the transistor and for the memory transistor,

producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,

producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,

producing at least one capacitor as part of the memory transistor,

producing a gate contact connected to the metal layer of the transistor, and

producing the gate contact connected to a metal layer of the capacitor of the memory transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2019
From: MUELLER, JOHANNES; POLAKOWSKI, PATRICK; DRESCHER, MAXIMILIAN; RIEDEL, STEFAN
To: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Reel/Frame 049094/0480 →
Priority Claims (1)
DE 10 2016 200 597 · Jan 19, 2016 · national
Continuity (2)
Continuation 15409818 · Jan 19, 2017
Related Publication 20190067297A1 · Feb 28, 2019