IP Library › Granted Patent US 11,055,464
Granted Patent B2
US 11,055,464 · App. 16/175,687 · Granted Jul 6, 2021

Critical dimension uniformity

Inventors: Chi-Ta Lu (Sanxing Township, TW); Chi-Ming Tsai (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G06F30/39G06F2111/06
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Quick Facts
Patent No.
US 11,055,464
App. No.
16/175,687
Granted
Jul 6, 2021
Kind
B2
Abstract

A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Claims (35)

1. A method comprising:

receiving a pattern layout for a mask;

shrinking the pattern layout to form a shrunk pattern;

determining centerlines for each of a plurality of features within the shrunk pattern;

snapping the centerline for each of the plurality of features to a grid, the grid representing a minimum resolution size of a mask fabrication tool; and

after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

2. The method of claim 1 , further comprising, adjusting a critical dimension of a feature of the plurality of features to meet a predetermined critical dimension.

3. The method of claim 2 , wherein the predetermined critical dimension is an integer multiple of the minimum resolution size of the mask fabrication tool.

4. The method of claim 1 , wherein the minimum resolution size of the mask fabrication tool is within a range of about 0.1 nanometers and 0.3 nanometers.

5. The method of claim 1 , wherein the minimum resolution size of the mask fabrication tool is about 0.2 nanometers.

6. The method of claim 1 , wherein the shrunk pattern has a size that is within 95-99 percent of a size of the pattern layout.

7. The method of claim 1 , wherein the shrunk pattern has a size that is about 98 percent of a size of the pattern layout.

8. The method of claim 1 , wherein snapping the centerline for each of the plurality of features to the grid comprises shifting a first subset of the plurality of features in a first direction perpendicular to the centerline and shifting a second subset of the plurality of features in a second direction opposite the first direction.

9. The method of claim 1 , wherein the snapping the centerlines for each of the plurality of features to the grid occurs after an OPC process.

10. The method of claim 1 , wherein the snapping the centerlines for each of the plurality of features to the grid occurs during a fracture process.

11. The method of claim 1 , further comprising, forming an integrated circuit using the mask.

12. A non-transitory computer readable medium comprising machine readable instructions that when executed by a processor cause a system to:

receive a mask pattern for fabrication of a layer in an integrated circuit;

shrink the mask pattern to form a shrunk pattern;

identify a centerline for a feature of the shrunk pattern;

snap the centerline of the feature to a grid, the grid representing a minimum resolution size of a mask fabrication tool; and

adjust a critical dimension of the feature to be an integer multiple of the minimum resolution size of the mask fabrication tool.

13. The non-transitory computer readable medium of claim 12 , wherein the machine readable instructions are further to transmit the shrunk pattern to a mask fabrication tool.

14. The non-transitory computer readable medium of claim 12 , wherein the mask fabrication tool is an e-beam lithography tool.

15. The non-transitory computer readable medium of claim 12 , wherein the system is further to identify centerlines for a plurality of features and snap the centerlines to the grid.

16. The non-transitory computer readable medium of claim 15 , wherein to snap the centerlines for the plurality of features to the grid, the system is to shift a first subset of the plurality of features in a first direction perpendicular to the centerlines and shift a second subset of the plurality of features in a second direction opposite the first direction.

17. A method comprising:

receiving a mask pattern for fabrication of a layer in an integrated circuit;

shrinking the mask pattern to form a shrunk pattern;

identifying a centerline for a feature of the shrunk pattern;

snapping the centerline of the feature to a grid, the grid representing a minimum resolution size of a mask fabrication tool; and

adjusting a critical dimension of the feature to be an integer multiple of the minimum resolution size of the mask fabrication tool.

18. The method of claim 17 , further comprising transmitting the shrunk pattern to a mask fabrication tool.

19. The method of claim 17 , wherein the mask fabrication tool is an e-beam lithography tool.

20. The method of claim 17 , further comprising identifying centerlines for a plurality of features and snap the centerlines to the grid.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2019
From: LU, CHI-TA; TSAI, CHI-MING
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 048899/0204 →
Continuity (2)
Provisional Application 62718805 · Aug 14, 2018
Related Publication 20200057833A1 · Feb 20, 2020