Flipped gate voltage reference and method of using
View Patent ↗A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.
1. A voltage reference comprising:
a flipped gate transistor coupled between an operating voltage node and a negative supply voltage node;
a first transistor and a second transistor coupled in series between the operating voltage node and the negative supply voltage node, wherein a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive a negative supply voltage of the negative supply voltage node;
an output node between the first transistor and the second transistor, the output node configured to output a reference voltage; and
a current source coupled between the output node and the negative supply voltage node in parallel with the second transistor, the current source configured to supply a current through the first transistor based on a current through the flipped gate transistor.
2. The voltage reference of claim 1 , wherein the flipped gate transistor is an n-type metal oxide semiconductor (NMOS) transistor and a gate electrode of the flipped gate transistor comprises a p-type dopant.
3. The voltage reference of claim 1 , wherein a bulk of the flipped gate transistor is connected to a source terminal of the flipped gate transistor.
4. The voltage reference of claim 1 , wherein a bulk of the first transistor is connected to a source terminal of the first transistor and a bulk of the second transistor is connected to a source terminal of the second transistor.
5. The voltage reference of claim 1 , wherein a bulk and a source terminal of the flipped gate transistor and a bulk, a gate, and a source terminal of the second transistor are connected to the negative supply voltage node.
6. The voltage reference of claim 1 , wherein an operating voltage of the operating voltage node has a value two times a value of the reference voltage.
7. The voltage reference of claim 1 , wherein
the current through the first transistor is a first integer multiple of a least common denominator,
the current through the flipped gate transistor is a second integer multiple of the least common denominator,
a size of the first transistor is a third integer multiple of a size of the flipped gate transistor, and
the first, second, and third integer multiples have a predetermined relationship to each other configured to cause the reference voltage to be a temperature-independent reference voltage.
8. A voltage reference comprising:
a flipped gate transistor coupled between an operating voltage node and a negative supply voltage node;
a first transistor and a second transistor coupled in series between the operating voltage node and the negative supply voltage node, wherein a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive a negative supply voltage of the negative supply voltage node;
an output node between the first transistor and the second transistor, the output node configured to output a reference voltage;
a current source coupled between the output node and the negative supply voltage node, the current source configured to supply a current through the first transistor related to a current through the flipped gate transistor; and
a third transistor in parallel with the first transistor and the second transistor, the third transistor configured to maintain a voltage drop across the first transistor approximately equal to the reference voltage.
9. The voltage reference of claim 8 , wherein each of the current through the first transistor and the current through the flipped gate transistor is a mirrored current based on a bias current.
10. The voltage reference of claim 9 , further comprising a bias current generator configured to generate the bias current based on the operating voltage.
11. The voltage reference of claim 9 , wherein the voltage reference is configured to receive the bias current from an external current source.
12. The voltage reference of claim 9 , wherein a current through the third transistor is based on a difference between the second current and a current mirrored from the bias current.
13. The voltage reference of claim 8 , wherein the third transistor is a first source follower configured to maintain a drain voltage of the first transistor at twice the reference voltage.
14. The voltage reference of claim 13 , further comprising a second source follower configured to bias a gate of the third transistor based on a voltage at a drain terminal of the flipped gate transistor.
15. A method of generating a reference voltage, the method comprising:
applying a first current to a flipped gate transistor;
generating a second current through a first transistor, the first transistor having a gate coupled with a gate of the flipped gate transistor;
generating a leakage current in a second transistor by applying a negative supply voltage to a gate and a source of the second transistor; and
outputting the reference voltage based on the first current and the leakage current flowing through the first transistor,
wherein the generating the second current comprises generating a third current using a current source in parallel with the second transistor.
16. The method of claim 15 , wherein the generating the second current further comprises adding the leakage current to the third current.
17. The method of claim 15 , wherein each of the applying the first current to the flipped gate transistor and the generating the third current using the current source comprises mirroring a bias current.
18. The method of claim 15 , wherein
the generating the second current through the first transistor further comprises applying the reference voltage to a bulk of the first transistor, and
the generating the leakage current in the second transistor comprises applying the negative supply voltage to a bulk of the second transistor.
19. The method of claim 15 , wherein the outputting the reference voltage comprises maintaining a drain voltage of the first transistor at twice the reference voltage using a pair of source followers.
20. The method of claim 15 , wherein the outputting the reference voltage comprises subtracting a gate-source voltage of the first transistor from a gate-source voltage of the flipped gate transistor.