Transient voltage suppression device
A transient voltage suppression device including a substrate and a first transient voltage suppressor is provided. The substrate includes a device region and a seal-ring region. The seal-ring region surrounds the device region. A first transient voltage suppressor is located in the device region. The first transient voltage suppressor includes a first well region having a first conductivity type, a first doped region having a second conductivity type, and a second doped region having the second conductivity type. The first well region is located in the substrate of the device region. The first doped region is located in the first well region. The second doped region is located in the first well region. A third doped region having the second conductivity type is located in the substrate of the seal-ring region, and the third doped region is electrically connected to the first doped region.
1. A transient voltage suppression device, comprising:
a substrate, comprising a device region and a seal-ring region, the seal-ring region surrounding the device region;
a first transient voltage suppressor, located in the device region, the first transient voltage suppressor comprising:
a first well region having a first conductivity type, located in substrate of the device region;
a first doped region having a second conductivity type, located in the first well region; and
a second doped region having the second conductivity type, located in the first well region; and
a third doped region having the second conductivity type, located in the substrate of the seal-ring region, wherein the third doped region is electrically connected to the first doped region.
2. The transient voltage suppression device as claimed in claim 1 , wherein the second doped region is located between the first doped region and the third doped region.
3. The transient voltage suppression device as claimed in claim 1 , wherein the first doped region, the second doped region, and the third doped region are separated from one another.
4. The transient voltage suppression device as claimed in claim 1 , wherein a gate structure is free from on the first well region between the first doped region and the second doped region.
5. The transient voltage suppression device as claimed in claim 1 , further comprising:
a second transient voltage suppressor, located in the device region, the second transient voltage suppressor comprising:
a second well region having the first conductivity type, located in substrate of the device region;
a fifth doped region having the second conductivity type, located in the second well region; and
a sixth doped region having the second conductivity type, located in the second well region; and
a seventh doped region having the second conductivity type, located in the substrate of the seal-ring region.
6. The transient voltage suppression device as claimed in claim 5 , wherein the first doped region, the third doped region, the fifth doped region, and the seventh doped region are electrically connected to a first voltage, the second doped region and the sixth doped region are electrically connected to a second voltage, and the first voltage and the second voltage are different.
7. The transient voltage suppression device as claimed in claim 5 , wherein the first doped region, the third doped region, and the sixth doped region are electrically connected to a first voltage, the second doped region, the fifth doped region, and the seventh doped region are electrically connected to a second voltage, and the first voltage and the second voltage are different.
8. The transient voltage suppression device as claimed in claim 1 , wherein the substrate further comprises a scribe line region, and the scribe line region is adjacent to the seal-ring region, wherein the seal-ring region is located between the device region and the scribe line region.
9. The transient voltage suppression device as claimed in claim 8 , further comprising a fourth doped region having the second conductivity type, the fourth doped region being located in the substrate of the scribe line region, wherein the fourth doped region is located aside and in contact with the third doped region.
10. The transient voltage suppression device as claimed in claim 9 , further comprising:
a metal layer, disposed on the substrate,
wherein the metal layer is free from on the fourth doped region.
11. The transient voltage suppression device as claimed in claim 5 , wherein the second transient voltage suppressor comprises a plurality of second transient voltage suppressors, and a plurality of the second well regions in the plurality of the second transient voltage suppressors are separated from one another and are not connected to one another.
12. The transient voltage suppression device as claimed in claim 5 , wherein the first transient voltage suppressor and the second transient voltage suppressor are Zener diodes with bi-directional discharge.
13. The transient voltage suppression device as claimed in claim 5 , wherein the first well region and the second well region are both electrically floating.
14. The transient voltage suppression device as claimed in claim 1 , wherein the substrate has the second conductivity type and is electrically floating.