IP Library Granted Patent US 10,566,994
Granted Patent B2
US 10,566,994 · App. 16/180,591 · Granted Feb 18, 2020

System and methods for virtualizing delta sigma digitization

Inventors: Belal Hamzeh (Westminster, CO); Zhensheng Jia (Superior, CO); Luis Alberto Campos (Superior, CO); Curtis Dean Knittle (Superior, CO); Jing Wang (Broomfield, CO)
Assignee: Cable Television Laboratories, Inc.
H03M3/496H03M3/424H03M3/43H04B10/58H04L12/2885H04B10/541
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Quick Facts
Patent No.
US 10,566,994
App. No.
16/180,591
Granted
Feb 18, 2020
Kind
B2
Abstract

A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels.

Claims (27)

1. A method for virtually performing delta-sigma digitization on a series of digital samples output from a communication stack of a communication network, the method comprising the steps of:

obtaining a delta-sigma digitization sampling frequency for the output series of digital samples;

calculating an oversampling ratio for the output series of digital samples;

interpolating the output series of digital samples at a rate equivalent to the oversampling ratio; and

quantizing the interpolated series of digital samples to a plurality of discrete predetermined levels,

wherein the output series of digital samples includes a number K digital samples from the communication stack, where K is an integer greater than 1,

wherein the oversampling ratio is represented by the symbol R, and

wherein a number of samples resulting from the step of interpolating is equal to R*K.

2. The method of claim 1 , wherein the step of interpolating and the step of quantizing are performed together as a single operation.

3. The method of claim 2 , wherein the step of quantizing is a binary operation.

4. The method of claim 3 , wherein at least two sequential samples of the output series of digital samples are processed at the same time.

5. The method of claim 4 , further comprising a sub step of assigning a linear interpolation between the two sequential samples.

6. The method of claim 1 , wherein the step quantizing is performed prior to the output series of digital samples being subject to digital-to-analog conversion.

7. The method of claim 6 , further comprising a step of transmitting the quantized digital samples in digital form to a receiver.

8. The method of claim 7 , wherein the receiver comprises a low pass filter.

9. A virtual delta-sigma digitization system for a communication network, the system including a processor in communication with a memory device configured to store a plurality of instructions, which, when executed by the processor, cause the processor to:

obtain a delta-sigma digitization sampling frequency for a series of digital samples output from a communication stack of the communication network, the output series of digital samples including K digital samples, where K is an integer greater than 1;

calculate an oversampling ratio, R, for the output series of digital samples;

interpolate the output series of digital samples at a rate equivalent to the oversampling ratio to generate a number of samples equal to R*K; and

quantize the interpolated series of digital samples to a plurality of discrete predetermined levels.

10. The system of claim 9 , wherein the processor is configured to interpolate and quantize the output series of digital samples as a single operation.

11. The system of claim 10 , wherein the instructions further cause the processor to quantize the output series of digital samples as a binary operation.

12. The system of claim 11 , wherein the instructions further cause the processor to process at least two sequential samples of the output series of digital samples simultaneously.

13. The system of claim 12 , wherein the instructions further cause the processor to assign a linear interpolation between the two sequential samples.

14. The system of claim 10 , wherein the instructions further cause the processor to quantize the output series of digital samples prior to converting the digital samples to an analog signal.

15. The system of claim 14 , wherein the instructions further cause the processor to transmit the quantized digital samples to a receiver in digital form.

16. The system of claim 15 , wherein the receiver comprises a low pass filter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2019
From: HAMZEH, BELAL; JIA, ZHENSHENG; CAMPOS, LUIS ALBERTO; KNITTLE, CURTIS DEAN; WANG, JING
To: CABLE TELEVISION LABORATORIES, INC
Reel/Frame 047930/0453 →
Continuity (6)
Continuation In Part 15875336 · Jan 19, 2018
Continuation In Part 15847417 · Dec 19, 2017
Provisional Application 62448044 · Jan 19, 2017
Provisional Application 62435961 · Dec 19, 2016
Provisional Application 62581166 · Nov 3, 2017
Related Publication 20190074846A1 · Mar 7, 2019