IP Library Granted Patent US 10,991,794
Granted Patent B2
US 10,991,794 · App. 16/181,786 · Granted Apr 27, 2021

Semiconductor device and method for manufacturing same

Inventor: Poren Tang (Beijing, CN)
Assignees: Semiconductor Manufacturing (Beijing) International Corporation; Semiconductor Manufacturing (Shanghai) International Corporation
H01L29/0649H01L21/7682H01L29/41775H01L29/4991H01L29/6653H01L29/66575H01L21/764H01L29/78
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Quick Facts
Patent No.
US 10,991,794
App. No.
16/181,786
Granted
Apr 27, 2021
Kind
B2
Abstract

The present specification discloses a semiconductor device and a method for manufacturing same. In one implementation, the method may include: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a gate structure disposed on the substrate, initial spacer layers on side surfaces of two sides of the gate structure, and a first inter-layer dielectric layer covering the gate structure and the initial spacer layers; and the substrate includes a source and a drain respectively located on the two sides of the gate structure; etching the first inter-layer dielectric layer to form a source contact hole and a drain contact hole that expose a part of the initial spacer layer; removing the exposed part of the initial spacer layer to expose the side surface of the gate structure; forming a spacer structure layer on the exposed side surface of the gate structure; forming a source contact member and a drain contact member in the contact holes; selectively removing at least a part of the spacer structure layer to form an air gap; and forming a second inter-layer dielectric layer covering the air gap. In the present invention, an air gap spacer structure can be formed and parasitic capacitance is reduced.

Claims (37)

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor structure, wherein the semiconductor structure comprises:

a substrate,

a gate structure disposed on the substrate,

initial spacer layers on side surfaces of two sides of the gate structure, and

a first inter-layer dielectric layer covering the gate structure and the initial spacer layers,

wherein the substrate comprises a source and a drain respectively located on the two sides of the gate structure;

etching the first inter-layer dielectric layer to form a source contact hole exposing the source and a drain contact hole exposing the drain, wherein the source contact hole and the drain contact hole further expose a part of the initial spacer layer on at least one side of the gate structure;

removing the exposed part of the initial spacer layer to expose the side surface of the at least one side of the gate structure;

forming a spacer structure layer on the exposed side surface of the at least one side of the gate structure, wherein:

the spacer structure layer comprises a first spacer layer, a sacrificial spacer layer, and a second spacer layer,

the first spacer layer is positioned between the gate structure and the sacrificial spacer layer, the sacrificial spacer layer is positioned between the first spacer layer and the second spacer layer, and a bottom end of the second spacer layer is higher than a bottom end of the first spacer layer, and

the first spacer layer is formed on the exposed side surface of the at least one side of the gate structure, the sacrificial spacer layer is formed on a side surface of the first spacer layer, and the second spacer layer is formed on a side surface of the sacrificial spacer layer;

after the spacer structure layer is formed, forming, in the source contact hole, a source contact member connected to the source, and forming, in the drain contact hole, a drain contact member connected to the drain;

after the source contact member and the drain contact member are formed, selectively removing the sacrificial spacer layer to form an air gap and maintaining the first spacer layer and the second spacer layer, wherein a bottom end of the air gap is positioned above the bottom end of the first spacer layer and below the bottom end of the second spacer layer; and

forming a second inter-layer dielectric layer on the first inter-layer dielectric layer, the source contact member, and the drain contact member, wherein the second inter-layer dielectric layer covers the air gap.

2. The method according to claim 1 , wherein:

in the step of forming the air gap, the air gap is formed between the gate structure and the source contact member or between the gate structure and the drain contact member.

3. The method according to claim 1 , wherein: in the step of forming the spacer structure layer, the sacrificial spacer layer is located on the exposed side surface of the at least one side of the gate structure.

4. The method according to claim 1 , wherein:

the material of the sacrificial spacer layer is different from the material of the first spacer layer.

5. The method according to claim 1 , wherein:

the material of the sacrificial spacer layer being different from the material of the second spacer layer.

6. The method according to claim 4 , wherein:

the material of the sacrificial spacer layer comprises SiON, SiOCN, amorphous silicon, or polysilicon.

7. The method according to claim 5 , wherein:

the materials of the first spacer layer and the materials of the second spacer layer respectively comprise SiN, SiON, or SiOCN; and

the material of the sacrificial spacer layer comprises polysilicon or amorphous silicon.

8. The method according to claim 1 , wherein:

the at least one side of the gate structure comprises the two sides of the gate structure.

9. The method according to claim 1 , wherein:

the step of forming the second inter-layer dielectric layer comprises non-conformally depositing the second inter-layer dielectric layer on the first inter-layer dielectric layer, the source contact member, and the drain contact member.

10. The method according to claim 1 , wherein:

in the step of providing the semiconductor structure, the gate structure comprises a gate insulation material layer on the substrate, a gate layer on the gate insulation material layer, and a hard mask layer on the gate layer; and

the first inter-layer dielectric layer is etched in self-alignment using the initial spacer layer to form the source contact hole and the drain contact hole.

11. The method according to claim 10 , further comprising:

forming a gate contact member running through the second inter-layer dielectric layer, the first inter-layer dielectric layer, and the hard mask layer and connected to the gate layer, wherein the gate contact member is spaced apart from the air gap in a horizontal direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2018
From: TANG, POREN
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION; SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Reel/Frame 047424/0563 →
Priority Claims (1)
CN 201711306991.6 · Dec 11, 2017 · national
Continuity (1)
Related Publication 20190181223A1 · Jun 13, 2019