Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip
An optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a p-doped region, an active region configured to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip, an n-doped region, a cover layer and a barrier region. The active region is arranged between the p-doped region and the n-doped region in a vertical direction, wherein the active region is based on a III-V semiconductor compound and the barrier region includes gallium, wherein the barrier region is configured to inhibit penetration of defects into the active region, and wherein the cover layer is arranged on the barrier region, the cover layer having a structured surface.
1. An optoelectronic semiconductor chip comprising:
a p-doped region;
an active region configured to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip, the active region having a main plane of extension;
an n-doped region;
a cover layer; and
a barrier region,
wherein the active region is arranged between the p-doped region and the n-doped region in a vertical direction, the vertical direction running perpendicular to the main plane of extension of the active region,
wherein the active region is based on a III-V semiconductor compound,
wherein the barrier region comprises gallium and extends parallel to the active region,
wherein the barrier region comprises a layer sequence comprising pairs of alternating layers, each pair comprising a first layer and a second layer, wherein the first layer and the second layer of each pair differ in an gallium concentration, and/or wherein at least one layer of each pair is either compressively stressed or tensioned,
wherein the barrier region is configured to inhibit penetration of defects into the active region, and
wherein the cover layer is arranged on the barrier region, the cover layer having a structured surface arranged at a side of the cover layer facing away from the barrier region.
2. The optoelectronic semiconductor chip according to claim 1 , wherein the barrier region is arranged between the active region and the structured surface of the cover layer in the vertical direction.
3. The optoelectronic semiconductor chip according to claim 1 , wherein the barrier region comprises aluminum at least in places.
4. The optoelectronic semiconductor chip according to claim 1 , wherein the barrier region comprises AlGaIn at least in places.
5. The optoelectronic semiconductor chip according to claim 1 , wherein the first layer and the second layer comprise gallium.
6. The optoelectronic semiconductor chip according to claim 1 , wherein either the first layer or the second layer is nominally free of gallium.
7. The optoelectronic semiconductor chip according to claim 1 , wherein one layer of each pair is compressively stressed and the respective other layer of each pair is tensioned.
8. The optoelectronic semiconductor chip according to claim 1 , wherein the first layer and the second layer of each pair differ in their an indium concentration.
9. An optoelectronic semiconductor chip comprising:
a p-doped region;
an active region configured to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip, the active region having a main plane of extension;
an n-doped region; and
a barrier region,
wherein the active region is arranged between the p-doped region and the n-doped region in a vertical direction, the vertical direction running perpendicular to the main plane of extension of the active region,
wherein the active region is based on a III-V semiconductor compound,
wherein the barrier region comprises gallium and extends parallel to the active region,
wherein the barrier region is configured to inhibit penetration of defects into the active region,
wherein the barrier region comprises a layer sequence comprising pairs of alternating layers, each pair comprising a first layer and a second layer, wherein the first layer and the second layer of each pair differ in an gallium concentration, and/or wherein at least one layer of each pair is either compressively stressed or tensioned.
10. The optoelectronic semiconductor chip according to claim 1 , wherein a thickness of the barrier region and a gallium concentration in the barrier region are selected such that a product of the thickness of the barrier region measured in μm and the gallium concentration in the barrier region in percent is at least 0.5.
11. The optoelectronic semiconductor chip according to claim 9 , wherein a thickness of the barrier region and a gallium concentration in the barrier region are selected such that a product of the thickness of the barrier region measured in μm and the gallium concentration in the barrier region in percent is at least 0.5.
12. The optoelectronic semiconductor chip according to claim 9 , wherein the first layer and the second layer comprise gallium.
13. The optoelectronic semiconductor chip according to claim 9 , wherein either the first layer or the second layer is nominally free of gallium.
14. The optoelectronic semiconductor chip according to claim 9 , wherein one layer of each pair is compressively stressed and the respective other layer of each pair is tensioned.
15. The optoelectronic semiconductor chip according to claim 9 , wherein the first layer and the second layer of each pair differ in an indium concentration.
16. The optoelectronic semiconductor chip according to claim 9 , wherein the optoelectronic semiconductor chip comprises a structured surface, and wherein the barrier region is arranged between the active region and the structured surface in the vertical direction.
17. The optoelectronic semiconductor chip according to claim 9 , wherein the barrier region comprises aluminum at least in places.
18. The optoelectronic semiconductor chip according to claim 9 , wherein the barrier region comprises AlGaIn at least in places.