High-speed signaling systems and methods with adaptable, continuous-time equalization

1. An integrated circuit comprising:

a single-ended port to receive an input signal from a channel affected by intersymbol interference (ISI), including first-post-cursor ISI and subsequent post-cursor ISI;

a continuous-time equalizer coupled to the single-ended port to produce a first equalized version of the input signal, the continuous-time equalizer including a first control port to control continuous-time equalization based upon a measure of the first-post-cursor ISI; and

a decision-feedback equalizer coupled to the continuous-time equalizer, the decision-feedback equalizer to produce, from the first equalized version of the input signal, a second equalized version of the input signal, the decision-feedback equalizer including a second control port to control decision-feedback equalization based upon a measure of the subsequent post-cursor ISI.

2. The integrated circuit of claim 1 , further comprising:

a first sampler to sample the second equalized version of the input signal to produce first samples;

a second sampler to sample the second equalized version of the input signal to produce second samples; and

an adaptation engine coupled to the first sampler and the second sampler to issue control signals to the first control port of the continuous-time equalizer responsive to the first samples and the second samples.

3. The integrated circuit of claim 2 , wherein the adaptation engine generates, from the first samples and the second samples, a tap value representative of first post-cursor inter-symbol interference in the input signal, and wherein the adaptation engine applies the tap value to the first control port.

4. The integrated circuit of claim 3 , wherein the adaptation engine generates, from the first samples and the second samples, a second tap value representative of second post-cursor inter-symbol interference for the input signal, and wherein the adaptation engine applies the second tap value to the second control port.

5. The integrated circuit of claim 2 , the continuous-time equalizer exhibiting a low-frequency gain and a peaking response, the adaptation engine to adjust the low-frequency gain responsive to comparisons between the first samples and the second samples.

6. The integrated circuit of claim 2 , the continuous-time equalizer exhibiting a low-frequency gain and a peaking response, the adaptation engine to adjust the low-frequency gain in dependence on the first samples and corresponding ones of the second samples.

7. The integrated circuit of claim 1 , the input signal comprising a series of symbols, the decision-feedback equalizer to reduce the intersymbol interference only from symbols other than the most-recently received symbol in the series of symbols.

8. The integrated circuit of claim 1 , wherein the continuous-time equalizer exhibits at least one of frequency-selective amplification and frequency-selective attenuation.

9. A method comprising:

receiving a single-ended input signal effected by intersymbol interference (ISI), including first-post-cursor ISI and subsequent post-cursor ISI;

measuring the first-post-cursor ISI and the subsequent post-cursor ISI;

applying continuous-time equalization to the single-ended input signal based on the measure of the first-post-cursor ISI to produce a first equalized continuous-time signal;

applying decision-feedback equalization to the first equalized continuous-time signal based on the measure of the subsequent post-cursor ISI to produce a second equalized continuous-time signal.

10. The method of claim 9 , further comprising:

sampling the second equalized continuous-time signal to produce first samples; and

sampling the second equalized continuous-time signal to produce second samples;

wherein measuring the first-post-cursor ISI includes applying a least-mean squared algorithm to the first samples and the second samples.

11. The method of claim 10 , further comprising measuring DC attenuation of the input signal using the least-mean squared algorithm.

12. The method of claim 11 , further comprising controlling the continuous-time equalization responsive to the measures of DC attenuation.

13. The method of claim 11 , further comprising generating, from the first samples and the second samples, a tap value representative of the first post-cursor ISI.

14. The method of claim 13 , further comprising generating, from the first samples and the second samples, a second tap value representative of second post-cursor ISI and applying the second tap value to the decision-feedback equalization.

15. The method of claim 9 , the input signal expressing a series of symbols, the continuous-time equalization reducing intersymbol interference associated only with a most-recently received symbol in the series of symbols.

16. The method of claim 15 , the decision-feedback equalization reducing the intersymbol interference only from symbols other than the most-recently received symbol in the series of symbols.

17. The method of claim 9 , the continuous-time equalization providing at least one of frequency-selective amplification and frequency-selective attenuation.

18. An integrated circuit comprising:

a single-ended channel to communicate an input signal effected by intersymbol interference (ISI), including first-post-cursor ISI and subsequent post-cursor ISI;

a continuous-time equalizer coupled to the single-ended channel to produce a first equalized version of the input signal, the continuous-time equalizer including a first control port to control continuous-time equalization based upon a measure of the first-post-cursor ISI;

a decision-feedback equalizer coupled to the continuous-time equalizer, the decision-feedback equalizer to produce from the first equalized version of the input signal a second equalized version of the input signal, the decision-feedback equalizer including a second control port to control decision-feedback equalization based upon a measure of the subsequent post-cursor ISI; and

means for measuring the first post-cursor ISI and the subsequent post-cursor ISI.

19. The integrated circuit of claim 18 , wherein the means for measuring the first post-cursor ISI and the subsequent post-cursor ISI measures DC attenuation of the input signal.