Imaging system with a digital conversion circuit for generating a digital correlated signal sample and related imaging method
An example imaging system includes a digital conversion circuit and a plurality of pixel circuits each having a photodiode, a biasing circuit, a charge-to-voltage converter, and a switch. The photodiode is configured to generate charges in response to light or radiation. The biasing circuit includes an operational amplifier having an input signal port for receiving a bias reference signal which controls a bias current flowing through an internal circuit of the operational amplifier. The charge-to-voltage converter is configured to accumulate the charges drained by the biasing circuit and convert the accumulated charges into a corresponding output voltage. The switch configured to selectively couple the charge-to-voltage converter to at least one data line. The digital conversion circuit is configured to generate a digital correlated signal sample for each pixel circuit using a difference between a digital signal sample and a digital reset level sample.
1. An imaging system having a pixel array comprising:
a plurality of pixel circuits, each pixel circuit includes:
a photodiode configured to generate charges in response to light or radiation;
a biasing circuit comprising an operational amplifier, which includes an input signal port for receiving a bias reference signal that controls a bias current flowing through an internal circuit of the operational amplifier;
a first charge-to-voltage converter configured to accumulate the charges drained by the biasing circuit and convert the accumulated charges into the corresponding output voltage; and
a first switch configured to selectively couple the first charge-to-voltage converter to at least one data line, wherein the at least one data line is coupled to at least two pixel circuits in a column; and
a digital conversion circuit configured to generate a digital correlated signal sample for each pixel circuit using a difference between a digital signal sample and a digital reset level sample;
wherein for each pixel circuit:
the operational amplifier is configured to operate in a high power state with the bias current of a first value flowing through the internal circuit of the operational amplifier when the bias reference signal is set to a first level during a readout period of the photodiode so as to drain charges generated by the photodiode and provide a constant bias voltage across the photodiode; and
the operational amplifier is configured to operate in a low power state with the bias current of a second value flowing through the internal circuit of the operational amplifier when the bias reference signal is set to a second level during an image acquisition period of the photodiode so as to output an output signal and provide the constant bias voltage across the photodiode; and
the second value is smaller than the first value.
2. The imaging system of claim 1 , further comprising:
a column readout circuit coupled to a plurality of data lines, and the column readout circuit includes:
a signal sample processing circuit configured to read a signal sample for each at least one data line; and
a reset level sample processing circuit configured to read a reset level sample for each at least one data line.
3. The imaging system of claim 1 , wherein the digital conversion circuit further comprises:
a memory configured to store the digital reset level sample for each pixel circuit.
4. The imaging system of claim 3 , wherein the digital conversion circuit further comprises:
an analog-to-digital converter (A/D converter) configured to convert the signal sample to the digital signal sample and the reset level sample to the digital reset level sample for each pixel circuit, wherein the A/D converter is coupled to the column readout circuit and the memory; and
subtraction circuit configured to generate the digital correlated signal sample for each pixel circuit using the difference of the digital reset level sample from the digital signal sample, wherein the subtraction circuit is coupled to the A/D converter and the memory.
5. The imaging system of claim 1 , wherein the digital conversion circuit further comprises:
an analog-to-digital converter (A/D converter) coupled to a column readout circuit and configured to convert the reset level sample at a beginning of an image acquisition period to the digital reset level sample and convert the signal sample acquired at an end of the image acquisition period to the digital signal sample for each pixel circuit; and
subtraction circuit coupled to the A/D converter and configured to generate the digital correlated signal sample for each pixel circuit using the difference of the digital reset level sample from the digital signal sample.
6. The imaging system of claim 1 , wherein the each pixel circuit further comprises:
a gain-switching circuit configured to detect the output voltage and provide a second charge-to-voltage converter to accumulate the charges generated by the photodiode in response to the output voltage exceeding a threshold voltage.
7. The imaging system of claim 6 , wherein:
the gain-switching circuit comprises:
a voltage comparator configured to generate a select signal according to a difference between the output voltage and the threshold voltage; and
a select circuit configured to generate a latch signal associated with a logic level of the select signal; and
the second charge-to-voltage converter is selectively coupled in parallel with the first charge-to-voltage converter based on the latch signal.
8. The imaging system of claim 1 , wherein:
the first charge-to-voltage converter comprises:
a first end coupled to a cathode of the photodiode; and
a second end for outputting the output voltage; and
the operational amplifier comprises:
a non-inverting input end;
an inverting input end coupled to the cathode of the photodiode;
an output end coupled to the second end of the first charge-to-voltage converter; and
an input signal port for receiving the bias reference signal.
9. The imaging system of claim 1 , wherein each pixel circuit further comprises:
a second switch to reset the first charge-to-voltage converter.
10. The imaging system of claim 1 , further comprising:
a first processing circuit configured to:
acquire a first signal sample by reading an output voltage generated by the first charge-to-voltage converter in a first pixel circuit among the plurality of the pixels circuits before resetting the first charge-to-voltage converter in the first pixel circuit; and
acquire a second signal sample by reading an output voltage generated by the first charge-to-voltage converter in a second pixel circuit among the plurality of the pixels circuits before resetting the first charge-to-voltage converter in the second pixel circuit; and
a second processing circuit configured to:
acquire a first reset level sample by reading the output voltage generated by the first charge-to-voltage converter in the first pixel circuit after resetting the first charge-to-voltage converter in the first pixel circuit; and
acquire a second reset level sample by reading the output voltage generated by the first charge-to-voltage converter in the second pixel circuit after resetting the first charge-to-voltage converter in the second pixel circuit, wherein:
the first pixel circuit is arranged in an mth row and an nth column of the pixel array, m and n being positive integers; and
the second pixel circuit is arranged in an (m+1)th row and the nth column of the pixel array.
11. The imaging system of claim 1 , wherein the first charge-to-voltage converter is a capacitor.
12. The imaging system of claim 1 , wherein the constant bias voltage is zero.
13. An imaging method, comprising:
operating an operational amplifier in a high power state with high bias current flowing through an internal circuit of the operational amplifier during a reset period or a readout period of a photodiode so as to output an output signal and provide a constant bias voltage across the photodiode;
resetting a first charge-to-voltage converter during a reset period and prior to an image acquisition period;
acquiring a reset level sample associated with charges accumulated in the first charge-to-voltage converter during the reset period;
operating the operational amplifier in a low power state with low bias current flowing through the internal circuit of the operational amplifier during the image acquisition period of the photodiode so as to drain charges generated by the photodiode in response to light or radiation and provide a constant bias voltage across the photodiode;
accumulating the charges drained from the photodiode in the first charge-to-voltage converter and converting the accumulated charges into a corresponding output voltage during the image acquisition period;
acquiring a signal sample by reading the output voltage during the readout period subsequent to the image acquisition period, wherein a signal sample voltage is associated with the charges accumulated in the first charge-to-voltage converter during the image acquisition period; and
generating a digital correlated signal sample for the charge of the photodiode using a difference between a digital signal sample and a digital reset level sample.
14. The imaging method of claim 13 , further comprising:
converting the reset level sample, using an A/D converter, to the digital reset level sample;
storing the digital reset level sample before acquiring the signal sample and generating the digital signal sample; and
converting the signal sample, using the A/D converter, to the digital signal sample.
15. The imaging method of claim 13 , further comprising:
generating a video signal for a pixel array from the digital correlated signal sample of the photodiode.
16. An imaging system, comprising:
means for operating an operational amplifier in a low power state with low bias current flowing through an internal circuit of the operational amplifier during an image acquisition period of a photodiode so as to drain charges generated by the photodiode in response to light or radiation and provide a constant bias voltage across the photodiode;
means for operating the operational amplifier in a high power state with high bias current flowing through the internal circuit of the operational amplifier during a reset period or a readout period of the photodiode so as to generate an output signal and provide the constant bias voltage across the photodiode;
means for accumulating the charges drained from the photodiode and converting the accumulated charges into the corresponding output voltage during the image acquisition period; and
means for acquiring a signal sample by reading the output voltage during the readout period subsequent to the image acquisition period, wherein the signal sample voltage is associated with the charges accumulated by the means for accumulating the charges during the image acquisition period;
means for resetting the means for accumulating the charges during the reset period and prior to the image acquisition period;
means for acquiring a reset level sample associated with charges accumulated in the means for accumulating the charges during the reset period; and
means for generating a digital correlated signal sample for the charge of the photodiode using a difference between a digital value of the signal sample and a digital value of the reset level sample.
17. The imaging system of claim 16 , wherein the means for generating a digital correlated signal sample, further comprises:
means for storing the digital value of the reset level sample before acquiring the signal sample and generating the digital value of the signal sample.
18. The imaging system of claim 16 , wherein the means for generating a digital correlated signal sample, further comprises:
means for converting the signal sample to the digital signal sample and the reset level sample to the digital reset level sample for each pixel circuit.
19. The imaging system of claim 16 , further comprising:
means for generating a video signal for a pixel array from the digital correlated signal sample of the photodiode.