Digital signal routing circuit
An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
1. A digital routing core, comprising:
a plurality of digital signal processing blocks, wherein each of said digital signal processing blocks comprises a source port and a destination port, said digital signal processing blocks each being configurable to: receive streams of audio data samples at a respective sample clock rate at said destination port, process the received streams of audio data samples, and transmit the processed streams of audio data samples at said respective sample clock rate from said source port;
a clock generator configurable to generate at least a data clock; and
a router, comprising a router input and a router output, and being configurable to route audio data samples from the router input to the router output in response to said data clock;
a source selector comprising a plurality of source selector inputs and a source selector output, wherein the source selector inputs are configured to receive data from source ports, wherein the source selector output is connected to said router input, and wherein said source selector is configurable in response to a source selector control signal to couple any of said source ports to said router input;
a destination selector comprising a destination selector input and a plurality of destination selector outputs, wherein the destination selector input is connected to said router output, wherein the destination selector outputs are connected to said destination ports, and wherein the destination selector is configurable in response to a destination selector control signal to couple any one of said destination ports to said router output;
programmable storage circuitry configurable to store a plurality of configuration data sets, each one of said plurality of configuration data sets respectively defining a signal path and a respective data sample rate for the signal path, said signal path comprising a source port and a destination port, and the data sample rates of said signal paths being definable independently of each other; and
a controller coupled to said programmable storage circuitry, said source selector and said destination selector, said controller being configured to receive said plurality of configuration data sets and to control said source and destination selectors with respective source and destination selector control signals to establish on a time-division-multiplexed basis in response to said data clock each one of said defined signal paths within each period of a respective sample clock.
2. A digital routing core as claimed in claim 1 , further comprising:
a plurality of source buffers each respectively connected between a said source port and a said source selector input, each source buffer configurable to temporarily store a sample of a respective stream of said audio data samples.
3. A digital routing core as claimed in claim 1 , further comprising:
a plurality of destination buffers each respectively connected between a said destination port and a said destination selector output, each destination buffer being configurable to temporarily store a sample of a respective stream of said audio data samples.
4. A digital routing core as claimed in claim 1 , further comprising a plurality of digital input interfaces, providing a further plurality of respective signal source ports.
5. A digital routing core as claimed in claim 1 , further comprising a plurality of digital output interfaces, providing a further plurality of respective signal destination ports.
6. A digital routing core as claimed in claim 1 , further comprising:
a plurality of digital input interfaces, providing a further plurality of respective signal source ports; and
a plurality of digital output interfaces, providing a further plurality of respective signal destination ports,
wherein the controller is configurable to define a direct signal path from one of said digital input interfaces through the router to one of said digital output interfaces.
7. A digital routing core as claimed in claim 1 , wherein the programmable storage circuitry is configurable to store at a single location data defining the sample rate for all destination ports on at least one signal processing block.
8. A digital routing core as claimed in claim 1 , wherein the programmable storage circuitry is configurable to store, for each signal path, data defining one of a predetermined number of available sample rates.
9. A digital routing core as claimed in claim 1 , wherein the controller comprises a router utilisation predictor, for identifying each defined signal path, for determining a number of calculations to be performed for each defined signal path in a specified time interval, and for setting the frequency of the data clock such that said number of calculations can be performed in the specified time interval.
10. A digital routing core as claimed in claim 9 , wherein the controller is adapted to receive inputs identifying a plurality of available data clock rates, and to select the frequency of the data clock as the lowest of these available data clock rates that enables said number of calculations to be performed in the specified time interval.
11. A digital routing core as claimed in claim 1 , wherein the controller is configured such that, at successive time intervals, the signal path that is established by the source and destination selector control signals is determined on the basis that it is the signal path that has the shortest time before an end of a period of a clock signal at the respective data sample rate.
12. A digital routing core as claimed in claim 11 , comprising a register, for storing details of activated signal paths, identifying the or each signal source port, the signal destination port, and the respective data sample rate of each activated signal path.
13. A digital routing core as claimed in claim 12 , comprising a down-counter associated with each available data sample rate, for maintaining a count of the time remaining before the end of a period of a clock signal at the respective data sample rate, and logic for selecting the sample rate having the shortest time before the end of a period of a clock signal at the respective data sample rate.
14. A digital routing core as claimed in claim 13 , further comprising logic for selecting one of the signal paths having the selected sample rate.
15. A digital routing core as claimed in claim 1 , further comprising:
at least one additional signal processing block, connected to receive digital input signals and to provide digital output signals without passing said signals through the router.
16. A digital routing core as claimed in claim 15 , comprising downsampling circuitry, for receiving the digital input signal of the additional signal processing block in parallel therewith, and for providing downsampled digital input signals at a signal source port comprised by the downsampling circuitry.
17. A digital routing core as claimed in claim 15 , comprising upsampling circuitry, comprising a signal destination port and for providing upsampled digital output signals.
18. A digital routing core as claimed in claim 15 , wherein the additional signal processing block is connected to receive control signals from at least one of a plurality of the first signal processing blocks.
19. A digital routing core as claimed in claim 15 , wherein the additional signal processing block comprises filter circuitry, for generating a noise cancellation signal from an input signal representing ambient noise.
20. A digital routing core as claimed in claim 1 , wherein the clock generator is configured for generating a plurality of clock signals at respective different frequencies; and
wherein the plurality of signal processing blocks each require a clock signal at a preferred frequency;
further comprising selection circuitry, configured such that each of the signal processing blocks receives said clock signal at the preferred frequency.