Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
A processing unit for a data processing system includes a cache memory having reservation logic and a processor core coupled to the cache memory. The processor includes an execution unit that executes instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads. The instructions include, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested. The processor core additionally includes a load unit that records the target address of the first load-reserve instruction and that, responsive to detecting, in the second hardware thread, a second load-reserve instruction identifying the target address recorded by the load unit, blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic.
1. A processing unit for a data processing system, said processing unit comprising:
a cache memory including reservation logic; and
a processor core coupled to the cache memory, the processor core comprising:
an execution unit that executes instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads, wherein the instructions include, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested; and
a load unit that records, within the processor core, the target address of the first load-reserve instruction, detects, in the second hardware thread, a second load-reserve instruction identifying the target address recorded by the load unit, and based on detection of the second load-reserve instruction, blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic of the cache memory.
2. The processing unit of claim 1 , wherein the load unit blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic by causing the processor core to discard execution results of the second load-reserve instruction.
3. The processing unit of claim 1 , wherein:
the load unit blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic by delaying issuance from the processor core to the cache memory of a load-reserve request corresponding to the second load-reserve instruction.
4. The processing unit of claim 1 , wherein the processor core includes a timer that determines a maximum duration of a protection interval for which the load unit blocks the second load-reserve instruction from obtaining a reservation for the target address in the reservation logic.
5. The processing unit of claim 1 , wherein the load unit ends a protection interval for which the load unit blocks the second load-reserve instruction from obtaining a reservation for the target address in the reservation logic based on detection of a third load-reserve instruction or a store-conditional instruction in the first hardware thread.
6. The processing unit of claim 1 , wherein the load unit, responsive to detecting in the second hardware thread a store-conditional instruction identifying the target address, blocks the store-conditional instruction from updating, in the cache memory, a memory location associated with the target address.
7. A data processing system, comprising:
multiple processing units, including the processing unit of claim 1 ;
a shared memory; and
a system interconnect communicatively coupling the shared memory and the multiple processing units.
8. The processing unit of claim 1 , wherein the load unit includes a blocking state machine that blocks the second load-reserve instruction from establishing a reservation.
9. A method of data processing in a processing unit of a data processing system, the processing unit including a processor core and a cache memory, said method comprising:
an execution unit of the processor core executing instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads, wherein the executing includes executing, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested;
a load unit of the processor core recording, within the processor core, the target address of the first load-reserve instruction; and
the load unit detecting in the second hardware thread a second load-reserve instruction identifying the target address recorded within the processor core by the load unit and, based on detecting the second load-reserve instruction, blocking the second load-reserve instruction from establishing a reservation for the target address in reservation logic of the cache memory.
10. The method of claim 9 , wherein the blocking includes the load unit blocking the second load-reserve instruction from establishing a reservation for the target address in the reservation logic by causing the processor core to discard execution results of the second load-reserve instruction.
11. The method of claim 9 , wherein the blocking includes the load unit blocking the second load-reserve instruction from establishing a reservation for the target address in the reservation logic by delaying issuance from the processor core to the cache memory of a load-reserve request corresponding to the second load-reserve instruction.
12. The method of claim 9 , wherein the processor core determining a maximum duration of a protection interval for which the load unit blocks the second load-reserve instruction from obtaining a reservation for the target address in the reservation logic by reference to a timer.
13. The method of claim 9 , and further comprising the load unit ending a protection interval for which the load unit blocks the second load-reserve instruction from obtaining a reservation for the target address in the reservation logic based on detection of a third load-reserve instruction or a store-conditional instruction in the first hardware thread.
14. The method of claim 9 , and further comprising the load unit, responsive to detecting in the second hardware thread a store-conditional instruction identifying the target address, blocks the store-conditional instruction from updating, in the cache memory, a memory location associated with the target address.
15. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a processing unit, including:
a cache memory including reservation logic; and
a processor core coupled to the cache memory, the processor core comprising:
an execution unit that executes instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads, wherein the instructions include, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested; and
a load unit that records, within the processor core, the target address of the first load-reserve instruction, detects, in the second hardware thread, a second load-reserve instruction identifying the target address recorded by the load unit, and based on detection of the second load-reserve instruction, blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic of the cache memory.
16. The design structure of claim 15 , wherein the load unit blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic by causing the processor core to discard execution results of the second load-reserve instruction.
17. The design structure of claim 15 , wherein:
the load unit blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic by delaying issuance from the processor core to the cache memory of a load-reserve request corresponding to the second load-reserve instruction.
18. The design structure of claim 15 , wherein the processor core includes a timer that determines a maximum duration of a protection interval for which the load unit blocks the second load-reserve instruction from obtaining a reservation for the target address in the reservation logic.
19. The design structure of claim 15 , wherein the load unit ends a protection interval for which the load unit blocks the second load-reserve instruction from obtaining a reservation for the target address in the reservation logic based on detection of a third load-reserve instruction or a store-conditional instruction in the first hardware thread.
20. The design structure of claim 15 , wherein the load unit, responsive to detecting in the second hardware thread a store-conditional instruction identifying the target address, blocks the store-conditional instruction from updating, in the cache memory, a memory location associated with the target address.