Balanced wideband impedance transformer
View Patent ↗A balanced wideband impedance transformer can include a first conductor layer including a first metal line and a second metal line, a second conductor layer including a first feed line and disposed on the first conductor layer, a third conductor layer including a second feed line and disposed on the second conductor layer, and a fourth conductor layer including a third metal line and a fourth metal line, and disposed on the third conductor layer.
1. A balanced wideband impedance transformer, comprising:
a first conductor layer including a first metal line and a second metal line;
a second conductor layer including a first feed line and disposed on the first conductor layer;
a third conductor layer including a second feed line and disposed on the second conductor layer; and
a fourth conductor layer including a third metal line and a fourth metal line, and disposed on the third conductor layer.
2. The balanced wideband impedance transformer according to claim 1 , each of the first to fourth metal lines being a perforated strip line.
3. The balanced wideband impedance transformer according to claim 1 , the first feed line being disposed between the first metal line and the third metal line, and the second feed line being disposed between the second metal line and the fourth metal line.
4. The balanced wideband impedance transformer according to claim 1 , the first feed line and the second feed line being configured to be respectively connected to a first phase signal and a second phase signal that is 180 degrees out of phase with the first phase signal, the first phase signal and the second phase signal having the same amplitude as each other.
5. The balanced wideband impedance transformer according to claim 1 , the first metal line being symmetric to the second metal line, and the third metal line being symmetric to the fourth metal line.
6. The balanced wideband impedance transformer according to claim 1 , each of the first feed line and the second feed line being configured to have a tapered width.
7. A unit cell of a dual polarized array, comprising:
the balanced wideband impedance transformer according to claim 1 ;
a first dipole connected to the first feed line; and
a second dipole connected to the second feed line.
8. The unit cell according to claim 7 , further comprising:
a substrate in which the first dipole and the second dipole are disposed;
a plurality of coupling metals disposed on a surface of the substrate; and
a plurality of frequency selective surface (FSS) superstrates disposed in the substrate.
9. A dual polarized array, comprising:
a plurality of unit cells, the plurality of unit cell including the unit cell according to claim 8 ; and
a ground plane connected to the first to fourth metal lines of each of the plurality of unit cells.
10. The dual polarized array according to claim 9 , the plurality of unit cells being arranged to form an egg-crate shape.
11. A balanced wideband impedance transformer, comprising:
a first perforated metal line and a second perforated metal line that are disposed at a first plane;
a third perforated metal line and a fourth perforated metal line that are disposed at a second plane;
a first feed line disposed between the first perforated metal line and the third perforated metal line; and
a second feed line disposed between the second perforated metal line and the fourth perforated metal line.
12. The balanced wideband impedance transformer according to claim 11 , further comprising a first dipole connected to the first feed line and a second dipole connected to the second feed line.
13. The balanced wideband impedance transformer according to claim 12 , further comprising a plurality of coupling metals corresponding to the first dipole and the second dipole.
14. The balanced wideband impedance transformer according to claim 13 , further comprising a substrate,
the first feed line, the second feed line, the first dipole, and the second dipole being located inside the substrate.
15. The balanced wideband impedance transformer according to claim 14 , further comprising a plurality of frequency selective surface (FSS) superstrates disposed inside the substrate.
16. The balanced wideband impedance transformer according to claim 15 , further comprising a ground plane connected to the first to fourth perforated metal lines.
17. The balanced wideband impedance transformer according to claim 16 , each of the first feed line and the second feed line being a tapered strip line.
18. The balanced wideband impedance transformer according to claim 17 , the first feed line and the second feed line being configured to be respectively connected to a first phase signal and a second phase signal that is 180 degrees out of phase with the first phase signal, the first phase signal and the second phase signal having the same amplitude as each other.
19. The balanced wideband impedance transformer according to claim 18 , further comprising a common plate connected to the first perforated metal line and the second perforated metal line.
20. A balanced wideband impedance transformer, comprising:
a substrate;
a first metal line and a second metal line that are disposed on a first surface of the substrate;
a third metal line and a fourth metal line that are disposed on a second surface of the substrate;
a first feed line disposed between the first metal line and the third metal line and disposed inside the substrate;
a second feed line disposed between the second metal line and the fourth metal line and disposed inside the substrate;
a first dipole connected to the first feed line and disposed inside the substrate;
a second dipole connected to the second feed line and disposed inside the substrate;
a plurality of frequency selective surface (FSS) superstrates disposed inside the substrate; and
a ground plane connected to the first to fourth metal lines,
the first dipole being placed between the first feed line and the FSS superstrates.