Active extensible memory hub

1. A semiconductor apparatus, comprising:

one or more substrates; and

a first extensible memory hub coupled to the one or more substrates, the first extensible memory hub including:

one or more upstream interface ports to couple the first extensible memory hub to a controller,

one or more downstream interface ports to couple the first extensible memory hub to one or more of nonvolatile memory or another extensible memory hub,

one or more bi-directional extension ports to be selectively configured to operate as an output port and an input port, the one or more bi-directional extension ports further being selectively configured to couple to another extensible memory hub and a second nonvolatile memory device, and

a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports to cause the one or more upstream interface ports to operate at the first frequency, provide a second clock signal at a second frequency to the one or more downstream interface ports to cause the one or more downstream interface ports to operate at the second frequency, and provide a third clock signal at a third frequency to the one or more bi-directional extension ports to cause the one or more bi-directional extension ports to operate at the third frequency,

wherein the first, second and third frequencies are to be different from each other.

2. The apparatus of claim 1 , wherein the first extensible memory hub further comprises:

a buffer coupled to the one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to actively manage the buffer for data transfer between the one or more upstream interface ports and the one or more downstream interface ports.

3. The apparatus of claim 2 , wherein the logic is further to actively manage the buffer for data transfer between the one or more bi-directional extension ports, the one or more upstream interface ports, and the one or more downstream interface ports.

4. The apparatus of claim 3 , wherein the logic is further to:

chain multiple extensible memory hubs with the one or more bi-directional extension ports.

5. The apparatus of claim 3 , wherein the logic is further to:

provide dual port access to the second nonvolatile memory device with the one or more bi-directional extension ports.

6. The apparatus of claim 3 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

7. An electronic memory system, comprising:

a controller;

nonvolatile memory; and

a first extensible memory hub communicatively coupled to the controller and the nonvolatile memory, the first extensible memory hub including:

one or more upstream interface ports to couple the first extensible memory hub to the controller,

one or more downstream interface ports to couple the first extensible memory hub to one or more of the nonvolatile memory or another extensible memory hub,

one or more bi-directional extension ports to be selectively configured to operate as an output port and an input port, the one or more bi-directional extension ports further being selectively configured to couple to another extensible memory hub and a second nonvolatile memory device, and

a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports to cause the one or more upstream interface ports to operate at the first frequency, provide a second clock signal at a second frequency to the one or more downstream interface ports to cause the one or more downstream interface ports to operate at the second frequency, and provide a third clock signal at a third frequency to the one or more bi-directional extension ports to cause the one or more bi-directional extension ports to operate at the third frequency,

wherein the first, second and third frequencies are to be different from each other.

8. The system of claim 7 , wherein the first extensible memory hub further comprises:

a buffer; and

logic to actively manage the buffer for data transfer between the one or more upstream interface ports and the one or more downstream interface ports.

9. The system of claim 8 , wherein the logic is further to actively manage the buffer for data transfer between the one or more bi-directional extension ports, the one or more upstream interface ports, and the one or more downstream interface ports.

10. The system of claim 9 , wherein the logic is further to:

chain multiple extensible memory hubs with the one or more bi-directional extension ports.

11. The system of claim 9 , wherein the logic is further to:

provide dual port access to the second nonvolatile memory device with the one or more bi-directional extension ports.

12. The system of claim 7 , wherein the nonvolatile memory comprises a solid state drive.

13. A method of extending memory, comprising:

providing one or more upstream interface ports to couple a first extensible memory hub to a controller;

providing one or more downstream interface ports to couple the first extensible memory hub to one or more of nonvolatile memory or another extensible memory hub;

providing one or more bi-directional extension ports to be selectively configured to operate as an output port and an input port, the one or more bi-directional extension ports further being selectively configured to couple to another extensible memory hub and a second nonvolatile memory device;

providing a first clock signal at a first frequency to the one or more upstream interface ports to cause the one or more upstream interface ports to operate at the first frequency;

providing a second clock signal at a second frequency to the one or more downstream interface ports to cause the one or more downstream interface ports to operate at the second frequency; and

providing a third clock signal at a third frequency to the one or more bi-directional extension ports to cause the one or more bi-directional extension ports to operate at the third frequency,

wherein the first, second and third frequencies are to be different from each other.

14. The method of claim 13 , further comprising:

actively managing data transfer between the one or more upstream interface ports and the one or more downstream interface ports.

15. The method of claim 14 , further comprising:

actively managing data transfer between the one or more bi-directional extension ports, the one or more upstream interface ports, and the one or more downstream interface ports.

16. The method of claim 15 , further comprising:

chaining multiple extensible memory hubs with the one or more bi-directional extension ports.

17. The method of claim 15 , further comprising:

providing dual port access to the second nonvolatile memory device with the one or more bi-directional extension ports.