Switch control circuit and buck converter including the same
A buck converter includes a power switch having one end to which an input voltage is transferred, a synchronous switch connected between the other end of the power switch and the ground, an inductor having an end connected to the other end of the power switch, and a switch control circuit configured to calculate a zero voltage delay time based on at least an ON time of the power switch and a delay time. The delay time is determined based on the inductor and parasitic capacitors of the power switch and the synchronous switch.
1. A switch control circuit for a power switch and a synchronous switch that are connected to an inductor, the switch control circuit comprising:
a comparator configured to compare a detection voltage obtained by detecting an inductor current flowing through the inductor with a predetermined reference voltage;
a delay unit configured to delay an output of the comparator by a zero voltage delay time; and
a zero voltage delay calculation unit configured to calculate the zero voltage delay time based on an ON time of the power switch, a given delay time, and a proportional constant, the proportional constant being proportional to a peak value of the inductor current,
wherein the given delay time is determined based on the inductor and a parasitic capacitor of the power switch and a parasitic capacitor of the synchronous switch.
2. The switch control circuit of claim 1 , wherein:
the switch control circuit is configured to control a peak current of the inductor current to be constant; and
the zero voltage delay calculation unit is configured to calculate the zero voltage delay time based on a comparison voltage corresponding to an output voltage generated by the inductor current, the given delay time, the proportional constant, and the ON time of the power switch.
3. The switch control circuit of claim 2 , wherein the zero voltage delay calculation unit is configured to calculate the zero voltage delay time based on the given delay time and a result of multiplying the comparison voltage, the proportional constant, and the given delay time and dividing the product by the ON time of the power switch.
4. The switch control circuit of claim 2 , wherein the zero voltage delay calculation unit is configured to calculate the zero voltage delay time by multiplying the proportional constant, the comparison voltage, and the given delay time, dividing the product by the ON time of the power switch, and adding the given delay time to the quotient.
5. The switch control circuit of claim 4 , wherein a product of the comparison voltage and the proportional constant is based on a result of dividing a product resulting from multiplying the peak current of the inductor current and an inductance of the inductor by the output voltage.
6. The switch control circuit of claim 4 , wherein:
the comparison voltage includes information regarding the peak current of the inductor current; and
information regarding the proportional constant is set by a node voltage between two resistors connected through a compensation pin of the switch control circuit.
7. The switch control circuit of claim 4 , further comprising:
first and second resistors coupled to each other at a node; and
a compensation pin coupled to the node and providing a signal indicative of the proportional constant to the zero voltage delay calculation unit.
8. The switch control circuit of claim 2 , wherein the zero voltage delay calculation unit comprises:
a multiplier multiplying the proportional constant, the comparison voltage, and the given delay time;
a divider dividing an output of the multiplier by the ON time of the power switch; and
an adder adding the given delay time to an output of the divider to calculate the zero voltage delay time.
9. The switch control circuit of claim 1 , wherein:
the switch control circuit is configured to control the ON time of the power switch to be constant;
the zero voltage delay calculation unit is configured to calculate the zero voltage delay time based on the ON time of the power switch, the given delay time, the proportional constant, and a detection voltage peak; and
the detection voltage peak is a peak of the detection voltage for each switching period of the power switch.
10. The switch control circuit of claim 9 , wherein the zero voltage delay calculation unit is configured to calculate the zero voltage delay time by multiplying the proportional constant, the detection voltage peak, and the given delay time, dividing the product by the ON time, and adding the given delay time to the quotient.
11. The switch control circuit of claim 10 , wherein a product of the detection voltage peak and the proportional constant is based on a result of dividing a product resulting from multiplying a peak current of the inductor current and an inductance of the inductor by an output voltage.
12. The switch control circuit of claim 10 , wherein:
the detection voltage peak includes information regarding a peak current of the inductor current; and
information regarding the proportional constant is set by a node voltage between two resistors connected through a compensation pin of the switch control circuit.
13. The switch control circuit of claim 9 , wherein:
the zero voltage delay calculation unit is configured to calculate the zero voltage delay time by multiplying the proportional constant, the detection voltage peak, and the given delay time, dividing the product by a comparison voltage, and adding the given delay time to the quotient; and
the comparison voltage corresponds to an output voltage generated by the inductor current.
14. The switch control circuit of claim 10 , further comprising:
first and second resistors coupled to each other at a node; and
a compensation pin coupled to the node and providing a signal indicative of the proportional constant to the zero voltage delay calculation unit.
15. The switch control circuit of claim 9 , wherein the zero voltage delay calculation unit comprises:
a multiplier multiplying the proportional constant, the detection voltage peak, and the given delay time;
a divider dividing an output of the multiplier by a comparison voltage, the comparison voltage corresponding to an output voltage generated by the inductor current; and
an adder adding the given delay time to an output of the divider to calculate the zero voltage delay time.
16. The switch control circuit of claim 1 , further comprising a compensation pin coupled to a node that provides a signal indicative of the proportional constant.
17. A buck converter comprising:
a power switch having one end to receive an input voltage;
a synchronous switch connected between a second end of the power switch and ground;
an inductor having an end connected to the second end of the power switch; and
a switch control circuit configured to calculate a zero voltage delay time based on an ON time of the power switch, a given delay time, and a proportional constant, the proportional constant being proportional to a peak value of an inductor current flowing through the inductor,
wherein the given delay time is determined based on the inductor and a parasitic capacitor of the power switch and a parasitic capacitor of the synchronous switch.
18. The buck converter of claim 17 , wherein the switch control circuit is configured to control the ON time of the power switch to be constant and calculate the zero voltage delay time based on the ON time of the power switch, the given delay time, the proportional constant, and a value corresponding to a peak current of the inductor current.
19. A method of operating a switch control circuit for a power switch and a synchronous switch that are coupled to an inductor, the method comprising:
comparing a detection voltage obtained by detecting an inductor current flowing through the inductor with a predetermined reference voltage;
calculating a zero voltage delay time based on an ON time of the power switch, a given delay time, and a proportional constant, the proportional constant being proportional to a peak value of the inductor current; and
delaying an output signal indicative of the comparison result by the zero voltage delay time,
wherein the given delay time is determined based on the inductor and a parasitic capacitor of the power switch and a parasitic capacitor of the synchronous switch.
20. The method of claim 19 , further comprising control a peak current of the inductor current to be constant,
wherein calculating the zero voltage delay time includes multiplying a comparison voltage, the proportional constant, and the given delay time and dividing the product by the ON time of the power switch, the comparison voltage corresponding to an output voltage generated by the inductor current.