Manufacturing method of a semiconductor device and method for creating a layout thereof
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
1. A semiconductor device comprising:
a first line extending in a first direction as viewed from above;
a second line extending in the first direction as viewed from above;
a dummy area provided between the first line and the second line, the dummy area including first, second, third, and fourth electrically isolated conductors, the first, second, and third electrically isolated conductors being arranged in the first direction and being closer to the first line than the second line, the second and fourth electrically isolated conductors being arranged in a second direction orthogonal to the first direction and being closer to the second line than the first line, shapes of the first, third, and fourth electrically isolated conductors being substantially the same, a shape of the second electrically isolated conductor being different from each of the shapes of the first, third, and fourth electrically isolated conductors.
2. The semiconductor device according to claim 1 , wherein
the shapes of the first, third, and fourth electrically isolated conductors are geometrically similar to one another, and
the shape of the second electrically isolated conductor is geometrically different from each of the shapes of the first, third, and fourth electrically isolated conductors.
3. The semiconductor device according to claim 1 , wherein
the dummy area further includes fifth, sixth, and seventh electrically isolated conductors, the fifth, sixth, and seventh electrically isolated conductors being arranged in the first direction and being closer to the second line than the first line, shapes of the fifth and seventh electrically isolated conductors being substantially the same with those of the first, third, and fourth electrically isolated conductors, the shape of the sixth electrically isolated conductor being different from each of the shapes of the first, third, fourth, fifth, and seventh electrically isolated conductors.
4. The semiconductor device according to claim 3 , wherein
the shapes of the first, third, fourth, fifth, and seventh electrically isolated conductors are geometrically similar to one another, and
the shape of the second and sixth electrically isolated conductor are geometrically similar to each other.
5. The semiconductor device according to claim 1 , wherein the first line and the second line are functioning lines.
6. The semiconductor device according to claim 1 , wherein the first line and the second line are conductive lines.
7. The semiconductor device according to claim 1 , wherein the first to fourth electrically isolated conductors have shapes based on a sidewall transfer processing.
8. The semiconductor device according to claim 1 , wherein the first to fourth electrically isolated conductors include a detailed pattern exceeding resolution limits of optical lithography.
9. The semiconductor device according to claim 1 , wherein the semiconductor device is a NAND flash memory device.