ILD gap fill for memory device stack array
A dual interlayer dielectric material structure is located on a passivation dielectric material liner and entirely fills a gap located between each memory device stack of a plurality of memory device stacks. The dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.
1. A semiconductor structure comprising:
a plurality of electrically conductive structures embedded in an interconnect dielectric material layer and present in a memory device area;
a memory device stack located on a surface of each electrically conductive structure of the plurality of electrically conductive structures, wherein each memory device stack includes a bottom electrode, a memory device pillar and a top electrode;
a passivation dielectric material liner located laterally adjacent to each memory device stack and on a surface of the interconnect dielectric material layer; and
a dual interlayer dielectric material structure located on the passivation dielectric material liner and entirely filling a gap between each memory device stack, wherein the dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.
2. The semiconductor structure of claim 1 , wherein the first void free low-k ILD material is composed of a single ILD material having a low dielectric constant and an undulating top surface.
3. The semiconductor structure of claim 1 , wherein the first void free low-k interlayer dielectric (ILD) material is composed of a void filling low-k dielectric material filling an entirety of each void present in a first ILD material having a low dielectric constant.
4. The semiconductor structure of claim 3 , wherein the void filling low-k dielectric material is composed of a same low-k dielectric material as the first ILD material.
5. The semiconductor structure of claim 1 , wherein the surface of the interconnect dielectric material is an undulating surface.
6. The semiconductor structure of claim 1 , wherein the memory device pillar is a ferroelectric memory (FE) device pillar, a resistive random access memory (ReRAM) device pillar, a magnetoresistive random access memory (MRAM) device pillar, or a phase change random access memory (PRAM) device pillar.
7. The semiconductor structure of claim 1 , wherein the memory device pillar is a MRAM device pillar comprising a magnetic reference layer, a tunnel barrier layer, a magnetic free layer and a cap layer.
8. The semiconductor structure of claim 1 , wherein the bottom electrode and the top electrode are composed of a conductive material.
9. The semiconductor structure of claim 8 , wherein the conductive material comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN or any combination thereof.
10. The semiconductor structure of claim 1 , further comprising a plurality of second electrically conductive structures embedded in the second void free low-k ILD material of the dual interlayer dielectric material structure, wherein each second electrically conductive structure contacts a surface of one of the top electrodes of the memory device stacks.