Mitigation of side-channel attacks using small-overhead random pre-charging
An electronic device includes a combinational logic circuit, one or more state-sampling components, and protection circuitry. The combinational logic circuit has one or more inputs and one or more outputs. The state-sampling components are configured to sample the outputs of the combinational logic circuit at successive clock cycles. The protection circuitry is configured to protect the combinational logic circuit by, per clock cycle, starting to apply random data to the inputs of the combinational logic circuit a given time duration before a sampling time of the state-sampling components for that clock cycle, and, after applying the random data, switching to apply functional data to the inputs of the combinational logic circuit, to be sampled by the state-sampling components. A propagation delay, over any signal path via the combinational logic circuit, is no less than the given time duration.
1. An electronic device, comprising:
a combinational logic circuit, having one or more inputs and one or more outputs;
one or more state-sampling components, configured to sample the outputs of the combinational logic circuit at successive clock cycles; and
protection circuitry, configured to protect the combinational logic circuit by performing, per clock cycle:
starting to apply random data to the inputs of the combinational logic circuit a given time duration before a sampling time of the state-sampling components for that clock cycle; and
after applying the random data, switching to apply functional data to the inputs of the combinational logic circuit, to be sampled by the state-sampling components,
wherein a propagation delay, over any signal path via the combinational logic circuit between the inputs and the outputs, is no less than the given time duration by which a beginning of the random data precedes the sampling time of the state-sampling components.
2. The electronic device according to claim 1 , wherein both the random data and the functional data are provided as input to the state-sampling components, but, due to the propagation delay being no less than the given time duration, the state-sampling components sample only the functional data and not the random data.
3. The electronic device according to claim 1 , wherein the combinational logic has a hold-time margin that is set to be at least the given time duration.
4. The electronic device according to claim 3 , wherein the combinational logic comprises one or more delay elements inserted in one or more signal paths, for setting the hold-time margin to be at least the given time duration.
5. The electronic device according to claim 1 , wherein the electronic device comprises at least first and second cryptographic engines for performing cryptographic operations, and wherein the protection circuitry is configured to generate the random data using the first cryptographic engine while the first cryptographic engine is not used for performing the cryptographic operations, and to generate the random data using the second cryptographic engine while the second cryptographic engine is not used for performing the cryptographic operations.
6. The electronic device according to claim 1 , wherein the protection circuitry is configured to modify the random data multiple times per clock cycle.
7. The electronic device according to claim 1 , wherein a timing of applying the random data and the functional data is preconfigured in the electronic device based on an individual performance of the combinational logic.
8. The electronic device according to claim 1 , wherein the protection circuitry is configured to adaptively modify a timing of applying the random data and the functional data over time, based on actual performance of the combinational logic.
9. The electronic device according to claim 8 , wherein the protection circuitry is configured to adaptively modify the timing so as to maximize a duty-cycle of applying the random data.
10. The electronic device according to claim 1 , wherein the random data has completed propagation through all signal paths via the combinational logic circuit before subsequent functional data is applied to the inputs of the combinational logic circuit.
11. A method for protecting a combinational logic circuit having one or more inputs and one or more outputs, the method comprising:
sampling the outputs of the combinational logic circuit at successive clock cycles using one or more state-sampling components; and
protecting the combinational logic circuit by performing, per clock cycle:
starting to apply random data to the inputs of the combinational logic circuit a given time duration before a sampling time of the state-sampling components for that clock cycle; and
after applying the random data, switching to apply functional data to the inputs of the combinational logic circuit, to be sampled by the state-sampling components,
wherein a propagation delay, over any signal path via the combinational logic circuit between the inputs and the outputs, is no less than the given time duration by which a beginning of the random data precedes the sampling time of the state-sampling components.
12. The method according to claim 11 , wherein both the random data and the functional data are provided as input to the state-sampling components, but, due to the propagation delay being no less than the given time duration, the state-sampling components sample only the functional data and not the random data.
13. The method according to claim 11 , wherein the combinational logic has a hold-time margin that is set to be at least the given time duration.
14. The method according to claim 13 , wherein the combinational logic comprises one or more delay elements inserted in one or more signal paths, for setting the hold-time margin to be at least the given time duration.
15. The method according to claim 11 , wherein the electronic device comprises at least first and second cryptographic engines for performing cryptographic operations, and wherein generating the random data comprises generating the random data using the first cryptographic engine while the first cryptographic engine is not used for performing the cryptographic operations, and generating the random data using the second cryptographic engine while the second cryptographic engine is not used for performing the cryptographic operations.
16. The method according to claim 11 , and comprising modifying the random data multiple times per clock cycle.
17. The method according to claim 11 , and comprising preconfiguring, in the electronic device, a timing of applying the random data and the functional data based on an individual performance of the combinational logic.
18. The method according to claim 11 , and comprising adaptively modifying a timing of applying the random data and the functional data over time, based on actual performance of the combinational logic.
19. The method according to claim 18 , wherein adaptively modifying the timing comprises maximizing a duty-cycle of applying the random data.
20. The method according to claim 11 , wherein the random data has completed propagation through all signal paths via the combinational logic circuit before subsequent functional data is applied to the inputs of the combinational logic circuit.