Charge steering transmitter
Disclosed herein is circuitry that extends the charge-steering (CS) logic library with a 2:1 CS-multiplexor (MUX) cell that can be used in a tree fashion to compose a 2 N :1 CS-MUX. Also presented is the integration of 2 N :1 CS-MUX with conventional CMOS signals at a parallel input, and a current-mode driver at the serialized output. Also presented are a non-return-to-zero (NRZ) to RZ serializing transmitter, a charge-steering multiplexor (CSM) pre-driver, and a CSM transmitter.
1. A charge-steering multiplexor (CSM) comprising a first 2:1 multiplexor (MUX), wherein the first 2:1 MUX comprises:
a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) having a first source/drain (S/D) connected to a first reference voltage, a gate to accept a first clock signal (ck 1 ), and a second S/D;
a second PMOS having a first S/D connected to the first reference voltage, a gate to accept the first clock signal, and a second S/D;
a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) having a first S/D connected to the second S/D of the first PMOS, a gate to accept a binary level first parallel return-to-zero (RZ) digital signal (d 0 ), and a second S/D;
a second NMOS having a first S/D connected to the second S/D of the first NMOS, a gate to accept a binary level second parallel RZ digital signal (d 2 ), and a second S/D;
a third NMOS having a first S/D connected to the second S/D of the second NMOS, a gate to accept the first clock signal, and a second S/D;
a fourth NMOS having a first S/D connected to the second S/D of the third NMOS, a gate to accept an inverted first clock signal (ck 1 _bar), and a second S/D connected to a second reference voltage having a lower potential than the first reference voltage;
a fifth NMOS having a first S/D connected to the second S/D of the second PMOS, a gate to accept an inverted first parallel RZ digital signal (d 0 _bar), and a second S/D;
a sixth NMOS having a first S/D connected to the second S/D of the fifth NMOS, a gate to accept an inverted second parallel RZ digital signal (d 2 _bar), and a second S/D;
a seventh NMOS having a first S/D connected to the second S/D of the sixth NMOS, a gate to accept the first clock signal, and a second S/D connected to the second S/D of the third NMOS;
a first capacitor (C 1 ) having a first terminal connected to the second S/D of the first PMOS to supply a binary level inverted first serial RZ digital signal (d 02 _bar), and a second terminal connected to the second reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the second S/D of the second PMOS to supply a binary level first serial RZ digital signal (d 02 ), and a second terminal connected to the second reference voltage; and,
a third capacitor (C 3 ) having a first terminal connected to the second S/D of the third NMOS and a second terminal connected to the second reference voltage.
2. The CSM of claim 1 further comprising a second 2:1 MUX, the second 2:1 MUX comprising:
a first PMOS having a first S/D connected to the first reference voltage, a gate to accept the first inverted clock signal (ck 1 _bar), and a second S/D;
a second PMOS having a first S/D connected to the first reference voltage, a gate to accept the first inverted clock signal, and a second S/D;
a first NMOS having a first S/D connected to the second S/D of the first PMOS of the second 2:1 MUX, a gate to accept a binary level third parallel RZ digital signal (d 1 ) in phase with the first parallel RZ digital signal (d 0 ), and a second S/D;
a second NMOS having a first S/D connected to the second S/D of the first NMOS of the second 2:1 MUX, a gate to accept a binary level fourth parallel RZ digital signal (d 3 ) in phase with the second parallel RZ digital signal (d 2 ), and a second S/D;
a third NMOS having a first S/D connected to the second S/D of the second NMOS of the second 2:1 MUX, a gate to accept the first inverted clock signal, and a second S/D;
a fourth NMOS having a first S/D connected to the second S/D of the third NMOS of the second 2:1 MUX, a gate to accept the first clock signal, and a second S/D connected to the second reference voltage;
a fifth NMOS having a first S/D connected to the second S/D of the second PMOS of the second 2:1 MUX, a gate to accept a binary level inverted third parallel RZ digital signal (d 1 _bar), and a second S/D;
a sixth NMOS having a first S/D connected to the second S/D of the fifth NMOS of the second 2:1 MUX, a gate to accept a binary level inverted fourth parallel RZ digital signal (d 3 _bar), and a second S/D;
a seventh NMOS having a first S/D connected to the second S/D of the sixth NMOS of the second 2:1 MUX, a gate to accept the first inverted clock signal, and a second S/D connected to the second S/D of the third NMOS of the second 2:1 MUX;
a first capacitor (C 1 ) having a first terminal connected to the second S/D of the first PMOS of the second 2:1 MUX to supply a binary level inverted second serial RZ digital signal (d 13 _bar) complementary in phase to the first serial RZ digital signal (d 02 ), and a second terminal connected to the second reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the second S/D of the second PMOS of the second 2:1 MUX to supply a binary level second serial RZ digital signal (d 13 ), and a second terminal connected to the second reference voltage;
a third capacitor (C 3 ) having a first terminal connected to the second S/D of the third NMOS of the second 2:1 MUX and a second terminal connected to the second reference voltage;
the CSM further comprising a third 2:1 MUX, the third 2:1 MUX comprising:
a first PMOS having a S/D connected to the first reference voltage, a gate to accept a second clock signal (ck 2 ), and a second S/D, where the clock rate of the second clock signal is twice that of the first clock signal;
a second PMOS having a first S/D connected to the first reference voltage, a gate to accept the second clock signal, and a second S/D;
a first NMOS having a first S/D connected to the second S/D of the first PMOS of the second 2:1 MUX, a gate to accept the first serial RZ digital signal (d 02 ), and a second S/D;
a second NMOS having a first S/D connected to the second S/D of the first NMOS of the second 2:1 MUX, a gate to accept the second serial RZ digital signal (d 13 ), and a second S/D;
a third NMOS having a first S/D connected to the second S/D of the second NMOS of the second 2:1 MUX, a gate to accept the second clock signal, and a second S/D;
a fourth NMOS having a first S/D connected to the second S/D of the third NMOS of the second 2:1 MUX, a gate to accept an inverted second clock signal (ck 2 _bar), and a second S/D connected to the second reference voltage;
a fifth NMOS having a first S/D connected to the second S/D of the second PMOS of the second 2:1 MUX, a gate to accept the inverted first serial RZ digital signal (d 02 _bar), and a second S/D;
a sixth NMOS having a first S/D connected to the second S/D of the fifth NMOS of the second 2:1 MUX, a gate to accept an inverted second serial RZ digital signal (d 13 _bar), and a second S/D;
a seventh NMOS having a first S/D connected to the second S/D of the sixth NMOS of the second 2:1 MUX, a gate to accept the second clock signal, and a second S/D connected to the second S/D of the third NMOS of the second 2:1 MUX;
a first capacitor (C 1 ) having a first terminal connected to the second S/D of the first PMOS of the second 2:1 MUX to supply a binary level inverted third serial RZ digital signal (d 0123 _bar), and a second terminal connected to the second reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the second S/D of the second PMOS of the second 2:1 MUX to supply a binary level third serial RZ digital signal (d 0123 ), and a second terminal connected to the second reference voltage; and,
a third capacitor (C 3 ) having a first terminal connected to the second S/D of the third NMOS of the second 2:1 MUX and a second terminal connected to the second reference voltage.
3. A charge-steering multiplexor (CSM) comprising:
a first multiplexor (MUX) comprising:
a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) having a first source/drain (S/D), a gate to accept a first inverted clock signal (ck 1 _bar), and a second S/D connected to a first reference voltage;
a second NMOS having a first S/D, a gate to accept the first inverted clock signal, and a second S/D connected to the first reference voltage;
a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) having a first S/D, a gate to accept a binary level first parallel return-to-zero (RZ) digital signal (d 0 ), and a second S/D connected to the first S/D of the first NMOS;
a second PMOS having a first S/D, a gate to accept a binary level second parallel RZ digital signal (d 2 ), and a second S/D connected to the first S/D of the first PMOS;
a third PMOS having a first S/D, a gate to accept the first inverted clock signal, and a second S/D connected to the first S/D of the second PMOS;
a fourth PMOS having a first S/D connected to a second reference voltage having a higher potential than the first reference voltage, a gate to accept a first clock signal (ck 1 ), and a second S/D connected to the first S/D of the third PMOS;
a fifth PMOS having a first S/D, a gate to accept a binary level inverted first parallel RZ digital signal (d 0 _bar), and a second S/D connected to the first S/D of the second NMOS;
a sixth PMOS having a first S/D, a gate to accept a binary level inverted second parallel RZ digital signal (d 2 _bar), and a second S/D connected to the first S/D of the fifth PMOS;
a seventh PMOS having a first S/D connected to the first S/D of the third PMOS, a gate to accept the first inverted clock signal, and a second S/D connected to the first S/D of the sixth PMOS;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first NMOS to supply a binary level inverted first serial RZ digital signal (d 02 _bar), and a second terminal connected to the first reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the first S/D of the second NMOS to supply a binary level first serial RZ digital signal (d 02 ), and a second terminal connected to the first reference voltage; and,
a third capacitor (C 3 ) having a first terminal connected to the second reference voltage, and a second terminal connected to the first S/D of the third PMOS.
4. The CSM of claim 3 further comprising a second 2:1 MUX, the second 2:1 MUX comprising:
a first NMOS having a first S/D, a gate to accept the first clock signal (ck 1 ), and a second S/D connected to the first reference voltage;
a second NMOS having a first S/D, a gate to accept the first clock signal, and a second S/D connected to the first reference voltage;
a first PMOS having a first S/D, a gate to accept a binary level third parallel RZ digital signal (d 1 ), and a second S/D connected to the first S/D of the first NMOS of the second 2:1 MUX;
a second PMOS having a first S/D, a gate to accept a binary level fourth parallel RZ digital signal (d 3 ), and a second S/D connected to the first S/D of the first PMOS of the second 2:1 MUX;
a third PMOS having a first S/D, a gate to accept the first clock signal, and a second S/D connected to the first S/D of the second PMOS of the second 2:1 MUX;
a fourth PMOS having a first S/D connected to the second reference voltage having a higher potential than the first reference voltage, a gate to accept the first inverted clock signal (ck 1 _bar), and a second S/D connected to the first S/D of the third PMOS of the second 2:1 MUX;
a fifth PMOS having a first S/D, a gate to accept a binary level inverted third parallel RZ digital signal (d 1 _bar), and a second S/D connected to the first S/D of the second NMOS of the second 2:1 MUX;
a sixth PMOS having a first S/D, a gate to accept a binary level inverted fourth parallel RZ digital signal (d 3 _bar), and a second S/D connected to the first S/D of the fifth PMOS of the second 2:1 MUX;
a seventh PMOS having a first S/D connected to the first S/D of the third PMOS of the second 2:1 MUX, a gate to accept the first clock signal, and a second S/D connected to the first S/D of the sixth PMOS of the second 2:1 MUX;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first NMOS of the second 2:1 MUX to supply a binary level inverted second serial RZ digital signal (d 13 _bar), and a second terminal connected to the first reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the first S/D of the second NMOS of the second 2:1 MUX to supply a binary level second serial RZ digital signal (d 13 ), and a second terminal connected to the first reference voltage;
a third capacitor (C 3 ) having a first terminal connected to the second reference voltage, and a second terminal connected to the first S/D of the third PMOS of the second 2:1 MUX;
the CSM further comprising a third 2:1 MUX, the third 2:1 MUX comprising:
a first NMOS having a first S/D, a gate to accept the second inverted clock signal (ck 2 _bar), and a second S/D connected to the first reference voltage, where the clock rate of the second clock signal is twice that of the first clock signal;
a second NMOS having a first S/D, a gate to accept the second inverted clock signal (ck 2 _bar), and a second S/D connected to the first reference voltage;
a first PMOS having a first S/D, a gate to accept the first serial RZ digital signal (d 02 ), and a second S/D connected to the first S/D of the first NMOS of the second 2:1 MUX;
a second PMOS having a first S/D, a gate to accept the second serial RZ digital signal (d 13 ), and a second S/D connected to the first S/D of the first PMOS of the second 2:1 MUX;
a third PMOS having a first S/D, a gate to accept the second inverted clock signal, and a second S/D connected to the first S/D of the second PMOS of the second 2:1 MUX;
a fourth PMOS having a first S/D connected to the second reference voltage, a gate to accept the second clock signal (ck 2 ), and a second S/D connected to the first S/D of the third PMOS of the second 2:1 MUX;
a fifth PMOS having a first S/D, a gate to accept the inverted first serial RZ digital signal (d 02 _bar), and a second S/D connected to the first S/D of the second NMOS of the second 2:1 MUX;
a sixth PMOS having a first S/D, a gate to accept the inverted second serial RZ digital signal (d 13 _bar), and a second S/D connected to the first S/D of the fifth PMOS of the second 2:1 MUX;
a seventh PMOS having a first S/D connected to the first S/D of the third PMOS of the second 2:1 MUX, a gate to accept the second inverted clock signal, and a second S/D connected to the first S/D of the sixth PMOS of the second 2:1 MUX;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first NMOS of the second 2:1 MUX to supply a binary level inverted third serial RZ digital signal (d 0123 _bar), and a second terminal connected to the first reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the first S/D of the second NMOS of the second 2:1 MUX to supply a binary level third serial RZ digital signal (d 0123 ), and a second terminal connected to the first reference voltage; and,
a third capacitor (C 3 ) having a first terminal connected to the second reference voltage, and a second terminal connected to the first S/D of the third PMOS of the second 2:1 MUX.
5. A charge-steering multiplexor (CSM) transmitter comprising:
a first 2:1 multiplexor (MUX) comprising:
a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) having a first source/drain (S/D) connected to a first reference voltage, a gate to accept a first clock signal (ck 1 ), and a second S/D;
a second PMOS having a first S/D connected to the first reference voltage, a gate to accept the first clock signal, and a second S/D;
a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) having a first S/D connected to the second S/D of the first PMOS, a gate to accept a binary level first parallel return-to-zero (RZ) digital signal (do), and a second S/D;
a second NMOS having a first S/D connected to the second S/D of the first NMOS, a gate to accept a binary level second parallel RZ digital signal (d 2 ), and a second S/D;
a third NMOS having a first S/D connected to the second S/D of the second NMOS, a gate to accept the first clock signal, and a second S/D;
a fourth NMOS having a first S/D connected to the second S/D of the third NMOS, a gate to accept an inverted first clock signal (ck 1 _bar), and a second S/D connected to a second reference voltage having a lower potential than the first reference voltage;
a fifth NMOS having a first S/D connected to the second S/D of the second PMOS, a gate to accept an inverted first parallel RZ digital signal (d 0 _bar), and a second S/D;
a sixth NMOS having a first S/D connected to the second S/D of the fifth NMOS, a gate to accept an inverted second parallel RZ digital signal (d 2 _bar), and a second S/D;
a seventh NMOS having a first S/D connected to the second S/D of the sixth NMOS, a gate to accept the first clock signal, and a second S/D connected to a second S/D of the third NMOS;
a first capacitor (C 1 ) having a first terminal connected to the second S/D of the first PMOS to supply a binary level inverted first serial RZ digital signal (d 02 _bar), and a second terminal connected to the second reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the second S/D of the second PMOS to supply a binary level first serial RZ digital signal (d 02 ), and a second terminal connected to the second reference voltage; and,
a third capacitor (C 3 ) having a first terminal connected to the second S/D of the third NMOS and a second terminal connected to the second reference voltage;
a second 2:1 MUX comprising:
a first PMOS having a first S/D connected to the first reference voltage, a gate to accept the first inverted clock signal (ck 1 _bar), and a second S/D;
a second PMOS having a first S/D connected to the first reference voltage, a gate to accept the first inverted clock signal, and a second S/D;
a first NMOS having a first S/D connected to the second S/D of the first PMOS of the second 2:1 MUX, a gate to accept a binary level third parallel RZ digital signal (d 1 ) in phase with the first parallel RZ digital signal (d 0 ), and a second S/D;
a second NMOS having a first S/D connected to the second S/D of the first NMOS of the second 2:1 MUX, a gate to accept a binary level fourth parallel RZ digital signal (d 3 ) in phase with the second parallel RZ digital signal (d 2 ), and a second S/D;
a third NMOS having a first S/D connected to the second S/D of the second NMOS of the second 2:1 MUX, a gate to accept the first inverted clock signal, and a second S/D;
a fourth NMOS having a first S/D connected to the second S/D of the third NMOS of the second 2:1 MUX, a gate to accept the first clock signal, and a second S/D connected to the second reference voltage;
a fifth NMOS having a first S/D connected to the second S/D of the second PMOS of the second 2:1 MUX, a gate to accept a binary level inverted third parallel RZ digital signal (d 1 _bar), and a second S/D;
a sixth NMOS having a first S/D connected to the second S/D of the fifth NMOS of the second 2:1 MUX, a gate to accept a binary level inverted fourth parallel RZ digital signal (d 3 _bar), and a second S/D;
a seventh NMOS having a first S/D connected to the second S/D of the sixth NMOS of the second 2:1 MUX, a gate to accept the first inverted clock signal, and a second S/D connected to a second S/D of the third NMOS of the second 2:1 MUX;
a first capacitor (C 1 ) having a first terminal connected to the second S/D of the first PMOS of the second 2:1 MUX to supply a binary level inverted second serial RZ digital signal (d 13 _bar) complementary in phase to the first serial RZ digital signal (d 02 ), and a second terminal connected to the second reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the second S/D of the second PMOS of the second 2:1 MUX to supply a binary level second serial RZ digital signal (d 13 ), and a second terminal connected to the second reference voltage;
a third capacitor (C 3 ) having a first terminal connected to the second S/D of the third NMOS of the second 2:1 MUX and a second terminal connected to the second reference voltage;
a pre-driver comprising:
a first current source having a first terminal connected to the first reference voltage and a second terminal;
a first PMOS having a first S/D connected to the second terminal of the first current source, a gate to accept the first serial RZ digital signal (d 02 ), and a second S/D;
a second PMOS having a first S/D connected to the second terminal of the first current source, a gate to accept the second serial RZ digital signal (d 13 ), and a second S/D;
a third PMOS having a first S/D connected to the second terminal of the current source, a gate to accept the inverted first serial RZ digital signal (d 02 _bar), and a second S/D;
a fourth PMOS having a first S/D connected to the second terminal of the current source, a gate to accept the inverted second serial RZ digital signal (d 13 _bar), and a second S/D;
a first load having a first terminal connected to the second S/D of the second PMOS of the pre-driver to supply a binary level inverted third serial NRZ digital signal (d 0123 _bar), and a second terminal connected to the second reference voltage; and,
a second load having a first terminal connected to the second S/D of the fourth PMOS of the pre-driver to supply a binary level third serial NRZ digital signal (d 0123 ), and a second terminal connected to the second reference voltage.
6. The CSM transmitter of claim 5 further comprising:
a driver comprising:
a second current source having a first terminal connected to the first reference voltage, and a second terminal;
a seventh PMOS having a first S/D connected to the second terminal of the second current source, a gate to accept the inverted third serial NRZ digital signal (d 0123 _bar), and a second S/D;
an eighth PMOS having a first S/D connected to the second terminal of the second current source, a gate to accept the third serial NRZ digital signal (d 0123 ), and a second S/D;
a third load having a first terminal connected to the second S/D of the seventh PMOS to supply an amplified inverted third NRZ digital signal, and a second terminal connected to the second reference voltage; and,
a fourth load having a first terminal connected to the second S/D of the eighth PMOS to supply an amplified third NRZ digital signal, and a second terminal connected to the second reference voltage.
7. A charge-steering multiplexor (CSM) transmitter comprising:
a first 2:1 multiplexor (MUX) comprising:
a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) having a first source/drain (SID), a gate to accept a first inverted clock signal (ck 1 _bar), and a second S/D connected to a first reference voltage;
a second NMOS having a first S/D, a gate to accept the first inverted clock signal, and a second S/D connected to the first reference voltage;
a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) having a first S/D, a gate to accept a binary level first parallel return-to-zero (RZ) digital signal (do), and a second S/D connected to the first S/D of the first NMOS;
a second PMOS having a first S/D, a gate to accept a binary level second parallel RZ digital signal (d 2 ), and a second S/D connected to the first S/D of the first PMOS;
a third PMOS having a first S/D, a gate to accept the first inverted clock signal, and a second S/D connected to the first S/D of the second PMOS;
a fourth PMOS having a first S/D connected to a second reference voltage having a higher potential than the first reference voltage, a gate to accept a first clock signal (ck 1 ), and a second S/D connected to the first S/D of the third PMOS;
a fifth PMOS having a first S/D, a gate to accept a binary level inverted first parallel RZ digital signal (d 0 _bar), and a second S/D connected to the first S/D of the second NMOS;
a sixth PMOS having a first S/D, a gate to accept a binary level inverted second parallel RZ digital signal (d 2 _bar), and a second S/D connected to the first S/D of the fifth PMOS;
a seventh PMOS having a first S/D connected to the first S/D of the third PMOS, a gate to accept the first inverted clock signal, and a second S/D connected to the first S/D of the sixth PMOS;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first NMOS to supply a binary level inverted first serial RZ digital signal (d 02 _bar), and a second terminal connected to the first reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the first S/D of the second NMOS to supply a binary level first serial RZ digital signal (d 02 ), and a second terminal connected to the first reference voltage;
a third capacitor (C 3 ) having a first terminal connected to the second reference voltage, and a second terminal connected to the first S/D of the third PMOS;
a second 2:1 MUX comprising:
a first NMOS having a first S/D, a gate to accept the first clock signal (ck 1 ), and a second S/D connected to the first reference voltage;
a second NMOS having a first S/D, a gate to accept the first clock signal, and a second S/D connected to the first reference voltage;
a first PMOS having a first S/D, a gate to accept a binary level third parallel RZ digital signal (d 1 ), and a second S/D connected to the first S/D of the first NMOS of the second 2:1 MUX;
a second PMOS having a first S/D, a gate to accept a binary level fourth parallel RZ digital signal (d 3 ), and a second S/D connected to the first S/D of the first PMOS of the second 2:1 MUX;
a third PMOS having a first S/D, a gate to accept the first clock signal, and a second S/D connected to the first S/D of the second PMOS of the second 2:1 MUX;
a fourth PMOS having a first S/D connected to the second reference voltage having a higher potential than the first reference voltage, a gate to accept the first inverted clock signal (ck 1 _bar), and a second S/D connected to the first S/D of the third PMOS of the second 2:1 MUX;
a fifth PMOS having a first S/D, a gate to accept a binary level inverted third parallel RZ digital signal (d 1 _bar), and a second S/D connected to the first S/D of the second NMOS of the second 2:1 MUX;
a sixth PMOS having a first S/D, a gate to accept a binary level inverted fourth parallel RZ digital signal (d 3 _bar), and a second S/D connected to the first S/D of the fifth PMOS of the second 2:1 MUX;
a seventh PMOS having a first S/D connected to the first S/D of the third PMOS of the second 2:1 MUX, a gate to accept the first clock signal, and a second S/D connected to the first S/D of the sixth PMOS of the second 2:1 MUX;
a first capacitor (C 1 ) having a first terminal connected to the first S/D of the first NMOS of the second 2:1 MUX to supply a binary level inverted second serial RZ digital signal (d 13 _bar), and a second terminal connected to the first reference voltage;
a second capacitor (C 2 ) having a first terminal connected to the first S/D of the second NMOS of the second 2:1 MUX to supply a binary level second serial RZ digital signal (d 13 ), and a second terminal connected to the first reference voltage;
a third capacitor (C 3 ) having a first terminal connected to the second reference voltage, and a second terminal connected to the first S/D of the third PMOS of the second 2:1 MUX;
a pre-driver comprising:
a first load having a first terminal connected to the second reference voltage and a second terminal to supply a binary level inverted third serial NRZ digital signal (d 0123 _bar);
a second load having a first terminal connected to the second reference voltage and a second terminal to supply a binary level third serial NRZ digital signal (d 0123 ) a first NMOS having a first S/D connected to the second terminal of the first load, a gate to accept the second serial RZ digital signal (d 13 ), and a second S/D;
a second NMOS having a first S/D connected to the second terminal of the first load, a gate to accept the first serial RZ digital signal (d 02 ), and a second S/D;
a third NMOS having a first S/D connected to the second terminal of the second load, a gate to accept the inverted second serial RZ digital signal (d 13 _bar), and a second S/D;
a fourth NMOS having a first S/D connected to the second terminal of the second load, a gate to accept the inverted first serial RZ digital signal (d 02 _bar), and a second S/D; and
a first current source having a first terminal connected to the second S/D of the first, second, third, and fourth NMOSs of the pre-driver, and a second terminal connected to the first reference voltage.
8. The CSM transmitter of claim 7 further comprising:
a driver comprising:
a third load having a first terminal connected to the second reference voltage and a second terminal to supply an amplified inverted third NRZ digital signal;
a fourth load having a first terminal connected to the second reference voltage and a second terminal to supply an amplified third NRZ digital signal;
a first NMOS having a first S/D connected to the second terminal of the first load, a gate to accept the third serial NRZ digital signal (d 0123 ), and a second S/D;
a second NMOS having a first S/D connected to the second terminal of the second load, a gate to accept the inverted third serial RZ digital signal (d 0123 _bar), and a second S/D; and,
a second current source having a first terminal connected to the second S/D of the first and second NMOSs of the driver, and a second terminal connected of the first reference voltage.