Semiconductor device and method for manufacturing same
A semiconductor device includes first and second inspection mark regions having the same pattern including a plurality of overlay inspection marks, a first element region having a portion overlapping with the first inspection mark region, and a second element region having a portion overlapping with the second inspection mark region. The first and second element regions are adjacent to each other and have different areas. The first element region includes a first pattern aligned with a plurality of first overlay inspection marks. The second element region includes a second pattern aligned with a plurality of second overlay inspection marks.
1. A semiconductor device, comprising:
a first inspection mark region and a second inspection mark region having a same pattern including a plurality of overlay inspection marks;
a first element region having a portion overlapping with the first inspection mark region; and
a second element region having a portion overlapping with the second inspection mark region, wherein
the first element region and the second element region are adjacent to each other and have different areas,
the first element region includes a first pattern aligned with a plurality of first overlay inspection marks that are some of the overlay inspection marks, and
the second element region includes a second pattern aligned with a plurality of second overlay inspection marks that are some of the overlay inspection marks.
2. The semiconductor device of claim 1 , wherein
the first inspection mark region and the second inspection mark region are adjacent to each other,
the first overlay inspection marks are all disposed in the first inspection mark region, and
the second overlay inspection marks are all disposed in the second inspection mark region.
3. The semiconductor device of claim 2 , wherein
a total area of the first inspection mark region and the second inspection mark region is equal to a total area of the first element region and the second element region.
4. The semiconductor device of claim 2 , wherein
four corners of each of the first inspection mark region and the second inspection mark region each include at least two of the overlay inspection marks that are arranged side by side in an adjacent direction in which the first inspection mark region and the second inspection mark region are adjacent to each other; and a distance between centers of the two overlay inspection marks is about half of a difference between a size of the first element region or the second element region and a size of the first inspection mark region in the adjacent direction.
5. The semiconductor device of claim 2 , further comprising:
a third inspection mark region having a same pattern as that of the first inspection mark region, and being adjacent to the second inspection mark region on a side of the second inspection mark region remote from the first inspection mark region; and
a third element region having a portion overlapping with the third inspection mark region, and being adjacent to the second element region on a side of the second element region remote from the first element region, wherein
the third element region has a third pattern aligned with the overlay inspection marks disposed in the third inspection mark region.
6. The semiconductor device of claim 1 , wherein
the first inspection mark region and the second inspection mark region are spaced apart from each other,
the first overlay inspection marks are all disposed in the first inspection mark region, and
the second overlay inspection marks are disposed on both of the first inspection mark region and the second inspection mark region.
7. The semiconductor device of claim 6 , wherein
four corners of each of the first inspection mark region and the second inspection mark region each include at least two of the overlay inspection marks arranged side by side in a direction in which the first inspection mark region and the second inspection mark region are arranged side by side.
8. The semiconductor device of claim 6 , further comprising:
a fourth element region having a portion overlapping with the second inspection mark region and being adjacent to the second element region on a side of the second element region remote from the first element region, wherein
the fourth element region includes a fourth pattern aligned with the overlay inspection marks disposed in at least the second inspection mark region.
9. The semiconductor device of claim 1 , wherein
the first element region includes a third overlay inspection mark, and
the second element region includes a fourth overlay inspection mark, wherein
the semiconductor device further includes:
a fifth element region having a fifth pattern aligned with the third overlay inspection mark and having a portion overlapping with the first element region; and
a sixth element region having a sixth pattern aligned with the fourth overlay inspection mark, and having a portion overlapping with the second element region.
10. A method for manufacturing a semiconductor device, the method comprising:
exposing an inspection mark mask to form a first inspection mark region and a second inspection mark region having a same pattern including a plurality of overlay inspection marks;
exposing a first mask to form a first pattern, thereby forming a first element region having a portion overlapping with the first inspection mark region; and
exposing a second mask to form a second pattern, thereby forming a second element region having a portion overlapping with the second inspection mark region, wherein
the first element region and the second element region are adjacent to each other and have different areas,
in the forming of the first element region, the first mask is aligned with a plurality of first overlay inspection marks that are some of the overlay inspection marks, and
in the forming of the second element region, the second mask is aligned with a plurality of second overlay inspection marks that are some of the overlay inspection marks.
11. The method of claim 10 , wherein
the first inspection mark region and the second inspection mark region are adjacent to each other,
the first overlay inspection marks are disposed in the first inspection mark region, and
the second overlay inspection marks are disposed in the second inspection mark region.
12. The method of claim 11 , wherein
a total area of the first inspection mark region and the second inspection mark region is equal to a total area of the first element region and the second element region.
13. The method of claim 11 , wherein
four corners of each of the first inspection mark region and the second inspection mark region each include at least two of the overlay inspection marks that are arranged side by side in an adjacent direction in which the first inspection mark region and the second inspection mark region are adjacent to each other; and a distance between centers of the two overlay inspection marks is about half of a difference between a size of the first element region or the second element region and a size of the first inspection mark region, in the adjacent direction.
14. The method of claim 11 , further comprising:
exposing the inspection mark mask to form a third inspection mark region that is adjacent to the second inspection mark region on a side of the second inspection mark region remote from the first inspection mark region; and
exposing a third mask to form a third element region that has a portion overlapping with the third inspection mark region, wherein
in the forming of the third element region, the third mask is aligned with the overlay inspection marks disposed in the third inspection mark region.
15. The method of claim 10 , wherein
the first inspection mark region and the second inspection mark region are spaced apart from each other,
the first overlay inspection marks are disposed in the first inspection mark region, and
the second overlay inspection marks are disposed on both of the first inspection mark region and the second inspection mark region.
16. The method of claim 15 , wherein
four corners of each of the first inspection mark region and the second inspection mark region each include at least two of the overlay inspection marks, which are arranged side by side in a direction in which the first inspection mark region and the second inspection mark region are arranged side by side.
17. The method of claim 15 , further comprising:
exposing a fourth mask to form a fourth pattern, thereby forming a fourth element region having a portion overlapping with the second inspection mark region and being adjacent to the second element region on a side of the second element region remote from the first element region, wherein
in the forming of the fourth element region, the fourth mask is aligned with the overlay inspection marks disposed in the second inspection mark region.
18. The method of claim 10 , wherein
the first pattern formed in the first element region includes a third overlay inspection mark, and
the second pattern formed in the second element region includes a fourth overlay inspection mark,
the method further includes:
aligning a fifth mask with the third overlay inspection mark and exposing the fifth mask to form a fifth pattern, thereby forming a fifth element region having a portion overlapping with the first element region: and
aligning a sixth mask with the fourth overlay inspection mark and exposing the sixth mask to form a sixth pattern, thereby forming a sixth element region having a portion overlapping with the first element region.