Efficient frequency detectors for clock and data recovery circuits
A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
1. A frequency detector circuit comprising:
a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input;
a first circuit configured to generate a second edge output;
a second circuit configured to generate a third edge output; and
a combinational logic configured to:
output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high; and
output a DOWN output when the first edge output, the second edge output, and the third edge output are all low,
wherein the first circuit comprises a first delay circuit and the second circuit comprises a second delay circuit.
2. The frequency detector of claim 1 , wherein the combinational logic comprises:
a DOWN logic; and
an UP logic.
3. The frequency detector circuit of claim 1 , wherein the combination logic further comprises a selection circuit configured to convert the operation of the frequency detector to a phase detector according to a selection signal.
4. A frequency detector circuit comprising:
a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input;
a first circuit configured to generate a second edge output;
a second circuit configured to generate a third edge output; and
a combinational logic configured to:
output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high; and
output a DOWN output when the first edge output, the second edge output, and the third edge output are all low,
wherein the combinational logic comprises:
a DOWN logic; and
an UP logic, and
wherein the DOWN logic comprises:
an AND gate having a first input, a second input, and a third input;
a first inverter configured to receive the first edge output and connected to the first input;
a second inverter configured to receive the second edge output and connected to the second input; and
a third inverter configured to receive the third edge output and connected to the third input.
5. A frequency detector circuit comprising:
a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input;
a first circuit configured to generate a second edge output;
a second circuit configured to generate a third edge output; and
a combinational logic configured to:
output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high; and
output a DOWN output when the first edge output, the second edge output, and the third edge output are all low,
wherein the combinational logic comprises:
a DOWN logic; and
an UP logic, and
wherein the UP logic comprises:
a three input OR gate;
a first AND gate configured to receive the first edge output and the second edge output and provide a first output to a first input of the three input OR gate;
a second AND gate configured to receive the first edge output and the third edge output and provide a second output to a second input of the three input OR gate; and
a third AND gate configured to receive the second edge output and the third edge output and provide a third output to a third input of the three input OR gate.