Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.
1. A semiconductor device, comprising:
first semiconductor wires disposed over a substrate, each of the first semiconductor wires including a channel region;
a first source/drain region in contact with the first semiconductor wires;
a gate dielectric layer disposed on and wrapping around the channel region of each of the first semiconductor wires;
a gate electrode layer disposed on the gate dielectric layer and wrapping around the channel region;
first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region;
second insulating spacers disposed on the first insulating spacers in the spaces; and
air gaps disposed in the spaces, respectively,
wherein each of the air gaps is defined by the source/drain region, each of the first insulating spacers and each of the second insulating spacers disposed in each of the spaces, and
a lateral end of each of the first insulating spacers is located closer to the source/drain region than a lateral end of each of the second insulating spacers.
2. The semiconductor device of claim 1 , wherein the second insulating spacers are made of a low-k dielectric material.
3. The semiconductor device of claim 2 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiO 2 and SiN.
4. The semiconductor device of claim 1 , wherein each of the first insulating spacers has a V-shape cross section having a apex located closer to the gate electrode than the source/drain region.
5. The semiconductor device of claim 1 , wherein the first source/drain region and the gate electrode layer are separated by the first insulating spacers, the second insulating spacers, the air gaps and a gate dielectric layer.
6. The semiconductor device of claim 1 , wherein the first source/drain region is in contact with ends of the first semiconductor wires.
7. The semiconductor device of claim 1 , wherein the first source/drain region wraps around parts of the first semiconductor wires.
8. A semiconductor device, comprising:
first semiconductor wires disposed over a substrate, each of the first semiconductor wires having a channel region and a source/drain region;
a first source/drain epitaxial layer wrapping around the source/drain region of each of the first semiconductor wires;
a gate dielectric layer disposed on and wrapping around the channel region of each of the first semiconductor wires;
a gate electrode layer disposed on the gate dielectric layer and wrapping around the channel region;
first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region; and
air gaps disposed in the spaces, respectively.
9. The semiconductor device of claim 8 , wherein the first semiconductor wires are made of SiGe or Ge.
10. The semiconductor device of claim 8 , further comprising second insulating spacers disposed in the spaces, respectively.
11. The semiconductor device of claim 10 , wherein the air gaps are in contact with the first source/drain region.
12. The semiconductor device of claim 10 , wherein the second insulating spacers are made of a low-k dielectric material.
13. The semiconductor device of claim 12 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiO 2 and SiN.
14. The semiconductor device of claim 8 , wherein each of the first insulating spacers has a V-shape cross section having a apex located closer to the gate electrode than the source/drain region.
15. The semiconductor device of claim 8 , wherein the first source/drain region and the gate electrode layer are separated by the first insulating spacers, the air gaps and the gate dielectric layer.
16. A semiconductor device, comprising:
first semiconductor wires disposed over a substrate, each of the first semiconductor wires having a channel region and a source/drain region;
a first source/drain epitaxial layer disposed on the source/drain region of each of the first semiconductor wires;
a gate dielectric layer disposed on and wrapping around the channel region of each of the first semiconductor wires;
a gate electrode layer disposed on the gate dielectric layer and wrapping around the the channel region; and
first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region,
wherein each of the first insulating spacers has a V-shape cross section having a apex located closer to the gate electrode than the source/drain region.
17. The semiconductor device of claim 16 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiO 2 and SiN.
18. The semiconductor device of claim 17 , further comprising:
second insulating spacers disposed in the spaces, respectively.
19. The semiconductor device of claim 18 , wherein the second insulating spacers are made of at least one selected from the group consisting of SiOC and SiOCN.
20. The semiconductor device of claim 8 , wherein the first semiconductor wires pass through the first source/drain epitaxial layer.