IP Library › Granted Patent US 10,673,326
Granted Patent B2
US 10,673,326 · App. 16/202,006 · Granted Jun 2, 2020

Semiconductor device including boosting circuit with plural pump circuits

Inventor: Masayuki Otsuka (Kanagawa, JP)
Assignee: LAPIS SEMICONDUCTOR CO., LTD.
H02M3/073G11C5/145G11C16/30H01L23/5223H01L27/0629H02M2003/075H02M2003/076
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Quick Facts
Patent No.
US 10,673,326
App. No.
16/202,006
Granted
Jun 2, 2020
Kind
B2
Abstract

A semiconductor device including: a semiconductor substrate; at least one circuit block provided on a main surface of the semiconductor substrate and having a predetermined function; a wiring layer including plural metal layers that connect the circuit block; and plural capacitors including a first capacitor connected to the circuit block and that uses the plurality of metal layers, and a second capacitor that uses an active area disposed within the main surface of the semiconductor substrate, wherein at least one of the first capacitor and at least one of the second capacitor are stacked in a stacking direction of layers of the semiconductor.

Claims (17)

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of circuit blocks each provided on a main surface of the semiconductor substrate and each having a predetermined function;

a wiring layer including a plurality of metal layers that are stacked on the main surface of the semiconductor substrate; and

a plurality of capacitors including first capacitors comprising the plurality of metal layers, and second capacitors comprising an active area disposed within the main surface of the semiconductor substrate,

wherein at least one of the first capacitors and at least one of the second capacitors are stacked in a stacking direction of the plurality of metal layers.

2. The semiconductor device according to claim 1 , wherein a dielectric body configuring the first capacitors comprises a silicon oxynitride film.

3. The semiconductor device according to claim 1 , wherein:

each one of the circuit blocks is a boosting circuit that includes capacitors from among the first capacitors or capacitors from among the second capacitors, the boosting circuits being connected in series and successively boosting a voltage input thereto;

from among the boosting circuits connected in series, a boosting circuit at an initial stage and a predetermined number of the boosting circuits include first capacitors from among the first capacitors; and

from among the boosting circuits connected in series, remaining boosting circuits other than the boosting circuit at the initial stage and the predetermined number of the boosting circuits include second capacitors from among the second capacitors.

4. The semiconductor device according to claim 3 , wherein:

each of the plurality of boosting circuits includes a MOS transistor that controls charges that flow into the first capacitors or the second capacitors; and

the second capacitors comprise a MOS transistor having a gate oxide film as a dielectric body.

5. The semiconductor device according to claim 4 , wherein the second capacitors and the MOS transistor that controls charges are disposed in a same layer.

6. The semiconductor device according to claim 1 , wherein the first capacitors are MIM capacitors or MOM capacitors.

7. The semiconductor device according to claim 1 , further comprising at least one shielding layer, provided between the first capacitors and the second capacitors, that shields the first capacitors and the second capacitors from each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2018
From: OTSUKA, MASAYUKI
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 047597/0728 →
Priority Claims (1)
JP 2017-227002 · Nov 27, 2017 · national
Continuity (1)
Related Publication 20190165673A1 · May 30, 2019