Semiconductor devices and methods of forming same
The present disclosure relates to packaging of integrated circuit chips for semiconductor devices. More particularly, the present disclosure relates to packaging of multiple chips for silicon photonics devices. The present disclosure provides a semiconductor device including a photonic integrated circuit (PIC) chip, an inductor positioned over the PIC chip, and a transimpedance amplifier (TIA) chip positioned over the PIC chip. The inductor has a first terminal end and a second terminal end, and the first terminal end is connected to the PIC chip.
1. A semiconductor device comprising:
a photonic integrated circuit (PIC) chip;
an inductor positioned over the PIC chip, the inductor having first and second terminal ends, wherein the first terminal end is connected to the PIC chip; and
a transimpedance amplifier (TIA) chip positioned over the PIC chip and the inductor, the TIA chip having an input contact and an output contact, wherein the inductor is between the TIA chip and the PIC chip, the inductor comprising a body that extends beyond and is at least partially uncovered by the TIA chip, and wherein the input contact of the TIA chip is connected to the second terminal end of the inductor and the output contact of the TIA chip being distal from the inductor.
2. The device of claim 1 , wherein an input side of the TIA chip is positioned over the first and second terminal ends of the inductor.
3. The device of claim 2 , wherein the inductor is positioned within a multilayer dielectric body on the PIC chip, the multilayer dielectric body comprising a plurality of insulating layers.
4. The device of claim 3 , wherein the inductor comprises a body having a turning layer and a crossing layer, wherein the turning layer and the crossing layer are positioned in different insulating layers of the multilayer dielectric body.
5. The device of claim 3 , further comprising:
a plurality of ground vias positioned within the multilayer dielectric body and connected to the PIC chip, wherein the ground vias are spaced apart from one another and aligned in a fence-like structure.
6. The device of claim 5 , wherein the TIA chip is positioned over the plurality of ground vias and the plurality of ground vias are spaced apart from and positioned between the input and output contacts of the TIA chip.
7. The device of claim 6 , wherein the TIA chip further comprises one or more ground contacts positioned over the plurality of ground vias and connected thereto.
8. The device of claim 7 , wherein the input and output contacts are located at a periphery of the TIA chip.
9. The device of claim 3 , wherein the output contact of the TIA chip is connected to a conductive trace positioned within the multilayer dielectric body.
10. The device of claim 9 , further comprising:
a laminate substrate having a cavity, wherein the PIC chip is placed within the cavity of the laminate substrate; and
a conductive wire bridging the conductive trace to the laminate substrate.
11. A method of forming a semiconductor device comprising:
providing a PIC chip;
forming an inductor over the PIC chip, the inductor having a body and first and second terminal ends, and the first terminal end is connected to the PIC chip;
providing a TIA chip having an input contact and an output contact; and
positioning the TIA chip to have the input contact over and connecting with the second terminal end of the inductor, and to have the output contact of the TIA chip distal from the inductor, wherein the inductor being positioned between the TIA chip and the PIC chip and the body of the inductor being extended beyond and at least partially uncovered by the TIA chip.
12. The method of claim 11 , wherein forming the inductor over the PIC chip includes forming the inductor in a multilayer dielectric body on the PIC chip.
13. The method of claim 12 , wherein forming the inductor includes forming redistribution patterns in the multilayer dielectric body.
14. The method of claim 13 , wherein forming redistribution patterns in the multilayer dielectric body comprises forming a plurality of ground vias in the multilayer dielectric body, the plurality of ground vias is spaced apart from and positioned between the input and output contacts of the TIA chip, wherein the ground vias are spaced apart from one another and aligned in a fence-like structure.
15. The method of claim 14 , wherein positioning the TIA chip includes connecting the plurality of ground vias with ground contacts of the TIA chip.
16. The method of claim 15 , further comprising:
providing a laminate substrate having a cavity;
positioning the PIC chip within the cavity of the laminate substrate; and
bridging the laminate substrate to a conductive trace formed in the multilayer dielectric body.
17. A semiconductor device comprising:
a photonic integrated circuit (PIC) chip;
an inductor positioned over the PIC chip, the inductor having first and second terminal ends, wherein the first terminal end is connected to the PIC chip; and
a transimpedance amplifier (TIA) chip positioned over the PIC chip and the inductor, the TIA chip having an input contact and an output contact, wherein the inductor is between the TIA chip and the PIC chip, the inductor comprising a body having a turning layer and a crossing layer, and wherein the input contact of the TIA chip is connected to the second terminal end of the inductor and the output contact of the TIA chip being distal from the inductor.
18. The device of claim 17 , wherein the inductor is positioned within a multilayer dielectric body on the PIC chip, the multilayer dielectric body comprising a plurality of insulating layers, wherein the turning layer and the crossing layer are positioned in different insulating layers of the multilayer dielectric body.
19. The device of claim 17 , wherein the body of the inductor extends beyond and is at least partially uncovered by the TIA chip.