IP Library Granted Patent US 11,107,753
Granted Patent B2
US 11,107,753 · App. 16/203,072 · Granted Aug 31, 2021

Packaging structure for gallium nitride devices

Inventors: Stephen St. Germain (Gilbert, AZ); Roger Arbuthnot (Mesa, AZ); David Billings (Mesa, AZ); Andrew Celaya (Phoenix, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/4952H01L21/565H01L23/3157H01L23/64H01L25/0655H01L29/2003
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,107,753
App. No.
16/203,072
Granted
Aug 31, 2021
Kind
B2
Abstract

Implementations of semiconductor packages may include: a substrate having one or more traces on a first side and one or more traces on a second side of the substrate. The substrate may be rigid. The packages may include at least one die mechanically and electrically coupled to the first side of the substrate. The die may be a high voltage die. The package may include one or more traces along one or more edges of the substrate. The one or more traces along the one or more edges of the substrate provide electrical connectivity between the one or more traces on the first side of the substrate and the one or more traces on the second side of the substrate. The package may also include a molding compound encapsulating at least the first and the one or more edges of the ceramic substrate.

Claims (32)

1. A semiconductor package comprising:

a substrate comprising one or more traces on a first side and one or more traces on a second side of the substrate opposite the first side of the substrate, wherein the substrate is rigid;

at least one die mechanically and electrically coupled to the first side of the substrate, wherein the die is a high voltage die;

one or more traces extending fully across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and the second side; and

a molding compound covering at least the first side of the substrate and directly coupled to and covering the one or more traces that extend fully across the one or more external edges of the substrate;

wherein the one or more traces that extend fully across the one or more edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate.

2. The semiconductor package of claim 1 , wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof.

3. The semiconductor package of claim 1 , wherein the substrate is a direct bonded copper substrate.

4. The semiconductor package of claim 1 , wherein the die comprises gallium nitride (GaN).

5. The semiconductor package of claim 1 , further comprising one of a clip or two or more wirebonds electrically coupling the one or more die to the substrate.

6. The semiconductor package of claim 5 , wherein the clip comprises a thickness from a 3 mil to a 20 mil.

7. The semiconductor package of claim 1 , further comprising one or more copper pillars coupled to one of the first side or the second side of the substrate.

8. A semiconductor package comprising:

a ceramic substrate comprising one or more traces on a first side and one or more traces on a second side of the ceramic substrate opposite the first side of the ceramic substrate, wherein the ceramic substrate is rigid and electrically insulative;

at least one high voltage die mechanically and electrically coupled to the first side of the ceramic substrate;

one or more traces extending from the first side to the second side of the ceramic substrate across a full thickness of the ceramic substrate and completely across an external surface of the ceramic substrate located across the full thickness; and

a molding compound encapsulating at least the first side and fully encapsulating the one or more traces that extend completely across the external surface of the ceramic substrate;

wherein the molding compound is directly coupled to the one or more traces that extend completely across the external surface of the ceramic substrate; and

wherein the one or more traces that extend completely across the external surface of the ceramic substrate provide electrical connectivity between the one or more traces on the first side of the ceramic substrate and the one or more traces on the second side of the ceramic substrate.

9. The semiconductor package of claim 8 , wherein the ceramic substrate comprises one of aluminum nitride, aluminum oxide, or any combination thereof.

10. The semiconductor package of claim 8 , wherein the die comprises gallium nitride (GaN).

11. The semiconductor package of claim 8 , further comprising one of a clip of two or more wirebonds electrically coupling the one or more die to the ceramic substrate.

12. The semiconductor package of claim 11 , wherein the clip comprises a thickness from a 3 mil to a 20 mil.

13. The semiconductor package of claim 8 , further comprising one or more copper pillars coupled to one of the first side or the second side of the ceramic substrate.

14. A substrate for a semiconductor package, the substrate comprising:

one or more traces on a first side of a substrate and one or more traces on a second side of the substrate, the first side opposite the second side;

one or more traces extending across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and second side; and

an insulative molding compound directly coupled to and encapsulating the one or more traces extending across the full thickness of the substrate;

wherein the one or more traces that extend along the one or more external edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate.

15. The semiconductor package of claim 1 , wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof.

16. The semiconductor package of claim 1 , wherein the substrate is a direct bonded copper substrate.

17. The semiconductor package of claim 1 , wherein the molding compound is an insulative molding compound.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 048327, FRAME 0670 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064079/0001 →
SECURITY INTEREST Recorded Feb 13, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 048327/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2018
From: ST. GERMAIN, STEPHEN; ARBUTHNOT, ROGER; BILLINGS, DAVID; CELAYA, ANDREW
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 047611/0090 →