Selective film growth for bottom-up gap filling

1. An integrated circuit device comprising:

a semiconductor substrate;

isolation regions adjacent to a surface of the semiconductor substrate;

a first semiconductor seed layer between isolation regions, the first semiconductor seed layer comprising:

a first portion on a top surface of a portion of the semiconductor substrate; and

a second portion and a third portion on sidewalls of the isolation regions and connecting to the first portion, wherein top surfaces of the second portion and the third portion are lower than top surfaces of the isolation regions; and

a first semiconductor region between the second portion and the third portion of the first semiconductor seed layer, wherein the first semiconductor seed layer and the first semiconductor region have different compositions.

2. The integrated circuit device of claim 1 further comprising:

a second seed layer overlapping the first semiconductor region and the first semiconductor seed layer; and

a second semiconductor region over and contacting the second seed layer.

3. The integrated circuit device of claim 2 , wherein a portion of the second seed layer and a portion of the second semiconductor region are higher than top surfaces of the isolation regions to form a semiconductor fin.

4. The integrated circuit device of claim 2 , wherein an entirety of the second seed layer and an entirety of the second semiconductor region in combination form a part of a semiconductor fin protruding higher than the isolation regions, and the integrated circuit device further comprising:

a gate stack on a top surface and sidewalls of the semiconductor fin.

5. The integrated circuit device of claim 4 further comprising:

a source region and a drain region on opposite sides of the gate stack, wherein the second seed layer and the second semiconductor region extend from the source region to the drain region.

6. The integrated circuit device of claim 1 , wherein the first semiconductor seed layer comprises silicon, and is free from germanium therein.

7. The integrated circuit device of claim 1 , wherein the first semiconductor seed layer comprises silicon germanium.

8. The integrated circuit device of claim 1 , wherein the first semiconductor region has a top surface higher than a top edge of the second portion of the first semiconductor seed layer.

9. An integrated circuit device comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate; and

a plurality of semiconductor regions between the isolation regions, with an upper one of the plurality of semiconductor regions being overlapping a respective lower one of the plurality of semiconductor regions, wherein each of the plurality of semiconductor regions comprises:

a seed layer; and

an epitaxy semiconductor region over a bottom portion of the seed layer, wherein the seed layer and the epitaxy semiconductor region are formed of different semiconductor materials.

10. The integrated circuit device of claim 9 , wherein the seed layer comprises:

a bottom portion; and

sidewall portions over, and connected to opposite ends of, the bottom portion of the seed layer, wherein the epitaxy semiconductor region is between the sidewall portions of the seed layer.

11. The integrated circuit device of claim 9 , wherein the seed layer is formed of silicon, and the epitaxy semiconductor region is formed of silicon germanium.

12. The integrated circuit device of claim 9 , wherein the seed layer is formed of silicon germanium, and the epitaxy semiconductor region is formed of germanium.

13. The integrated circuit device of claim 9 , wherein a top one of the plurality of semiconductor regions is higher than top surfaces of the isolation regions to form a part of a semiconductor fin.

14. The integrated circuit device of claim 13 , wherein more than one of the plurality of semiconductor regions are higher than the top surfaces of the isolation regions.

15. The integrated circuit device of claim 13 further comprising a Fin Field-Effect Transistor (FinFET), with a portion of the plurality of semiconductor regions forming a channel region of the FinFET.

16. The integrated circuit device of claim 9 , wherein the plurality of semiconductor regions comprises a first semiconductor region and a second semiconductor region over and contacting the first semiconductor region, wherein the seed layer of the second semiconductor region is spaced apart from the seed layer of the first semiconductor region by the epitaxy semiconductor region of the first semiconductor region.

17. An integrated circuit device comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate; and

a semiconductor region between opposite portions of the isolation regions, the semiconductor region comprising:

a seed layer comprising:

a bottom portion; and

sidewall portions contacting sidewalls of the isolation regions, wherein the bottom portion and the sidewall portions form a basin; and

an epitaxy semiconductor region in the basin, wherein the epitaxy semiconductor region and the seed layer are formed of different semiconductor materials.

18. The integrated circuit device of claim 17 further comprising:

an additional semiconductor region over the semiconductor region, wherein the additional semiconductor region comprises:

a lower portion between, and at a same level as, the opposite portions of the isolation regions; and

an upper portion protruding higher than top surfaces of the isolation regions.

19. The integrated circuit device of claim 17 , wherein the epitaxy semiconductor region has a higher germanium percentage than the seed layer.

20. The integrated circuit device of claim 17 , wherein the seed layer has a higher silicon percentage than the epitaxy semiconductor region.