Simulation of exclusive instructions

1. A method for controlling execution of target program code on a host data processing apparatus to simulate execution of the target program code on a target processing apparatus, the method comprising:

in response to a load-exclusive instruction of the target program code for instructing the target processing apparatus to load a value from a memory location and tag the memory location as exclusive, mapping the load-exclusive instruction to a load instruction to be executed by the host data processing apparatus to load the value from the memory location, and storing metadata related to the load-exclusive instruction, wherein the metadata comprises at least the value loaded from the memory location; and

in response to a store-exclusive instruction of the target program code for instructing the target processing apparatus to determine whether the memory location is still tagged as exclusive and to write a store value to the specified memory location in response to determining that the memory location is still tagged as exclusive, emulating the store-exclusive instruction using an atomic compare-and-swap instruction to be executed by the host data processing apparatus;

the atomic compare-and-swap instruction specifying, as a compare value to be compared against the value stored at the memory location when the atomic compare-and-swap instruction is executed, the value loaded from the memory location as specified by the metadata.

2. A method according to claim 1 , wherein the store-exclusive instruction specifies the store value to be stored to the memory location, and

the method comprises specifying the store value of the store-exclusive instruction as a swap value to be stored at the memory location when a comparison between the compare value and the value stored at the memory location satisfies a predetermined condition when the atomic compare-and-swap instruction is executed.

3. A method according to claim 1 , comprising:

in response to a compare-and-swap fail indication indicating that a comparison between the compare value and the value stored at the memory location failed to satisfy a predetermined condition, returning a store-exclusive fail as a response to the store-exclusive instruction.

4. A method according to claim 1 , wherein the metadata is stored in a simulation control region of memory inaccessible to the target program code.

5. A method according to claim 1 , comprising:

in response to the store-exclusive instruction, performing a validity check to check the validity of the metadata; and

when the validity check fails, returning a store-exclusive fail as a response to the store-exclusive instruction.

6. A method according to claim 5 , wherein

the metadata comprises at least one of a memory address, a data size and a memory attribute specified by the load-exclusive instruction, and the validity check comprises checking whether the store-exclusive instruction specifies the same memory address, data size or memory attribute as the load-exclusive instruction.

7. A method according to claim 5 , wherein the validity check fails when an event indicative of a possible communication between the target program code and other program code has been detected in a period between the load instruction and the atomic compare-and-swap instruction.

8. A method according to claim 7 , wherein the event comprises an event other than a memory access to the memory location addressed by the load-exclusive instruction.

9. A method according to claim 5 , wherein the validity check fails when an exception has been detected in a period between the load instruction and the atomic compare-and-swap instruction.

10. A method according to claim 5 , wherein

in response to a store-exclusive-fail-triggering event, replacing a value of the metadata with a reserved value, and

in response to the store-exclusive instruction, detecting that the validity check fails when the metadata has the reserved value.

11. A method according to claim 5 , comprising:

when the validity check fails for a predetermined number of attempts to simulate the store-exclusive instruction using the atomic compare-and-swap instruction, triggering operation of an alternative method for simulating execution of the store-exclusive instruction.

12. A non-transitory, computer-readable storage medium storing a computer program for controlling a host data processing apparatus to perform the method of claim 1 .

13. An apparatus comprising:

host processing circuitry; and

control circuitry configured to control the host processing circuitry to carry out the method of claim 1 .

14. A computer program stored on a non-transitory, computer-readable storage medium, the computer program being for controlling execution of target program code on a host data processing apparatus to simulate execution of the target program code on a target processing apparatus, wherein the computer program comprises:

load-exclusive program logic to map, in response to a load-exclusive instruction of the target program code for instructing the target processing apparatus to load a value from a memory location and tag the memory location as exclusive, the load-exclusive instruction to a load instruction to be executed by the host data processing apparatus to load the value from the memory location, and to store metadata related to the load-exclusive instruction, wherein the metadata comprises at least the value loaded from the memory location; and

store-exclusive program logic responsive to a store-exclusive instruction of the target program code for instructing the target processing apparatus to determine whether the memory location is still tagged as exclusive and to write a store value to the specified memory location in response to determining that the memory location is still tagged as exclusive, to emulate the store-exclusive instruction using an atomic compare-and-swap instruction to be executed by the host data processing apparatus;

the atomic compare-and-swap instruction specifying, as a compare value to be compared against the value stored at the memory location when the atomic compare-and-swap instruction is executed, the value loaded from the memory location as specified by the metadata.