Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features
View Patent ↗Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.
1. A method of forming an integrated circuit, the method comprising the steps of:
forming a dielectric layer;
forming a bottom contact in the dielectric layer with an upper surface of the bottom contact exposed through an upper surface of the dielectric layer;
defining two sidewalls indented into the dielectric layer by recessing the bottom contact into the dielectric layer via selective etching, the two sidewalls bordering regions of the bottom contact removed during recessing;
forming two dielectric sidewall spacers along the two sidewalls;
forming a landing pad on the bottom contact between the two dielectric sidewall spacers, wherein the maximum width of the landing pad at the top surface of the landing pad is smaller than a width of the bottom contact at an interface between the landing pad and the bottom contact; and
forming an additional feature directly on top of the landing pad at least in part by anisotropic etching.
2. The method of claim 1 , wherein the dielectric layer comprises silicon oxide.
3. The method of claim 1 , wherein the bottom contact comprises at least one of copper, cobalt, ruthenium, or aluminum.
4. The method of claim 1 , wherein the bottom contact is formed at least in part by a damascene process.
5. The method of claim 1 , wherein the bottom contact is lined at least in part by a material having a different composition than a core of the bottom contact.
6. The method of claim 1 , wherein the recessing step comprises wet etching.
7. The method of claim 1 , wherein an additional bottom contact separate from the bottom contact is covered by one or more additional masking layers of material during the recessing step.
8. The method of claim 1 , wherein the two sidewall spacers comprise at least one of silicon nitride, silicon oxynitride, or nitrogen-doped silicon carbide.
9. The method of claim 1 , wherein the step of forming two sidewall spacers comprises the sub-steps of:
conformally depositing a dielectric material; and
anistropically etching the dielectric material to leave portions of the dielectric material along the two sidewalls.
10. The method of claim 1 , wherein the landing pad comprises at least one of niobium, niobium nitride tungsten, tungsten nitride, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or molybdenum.
11. The method of claim 1 , wherein the step of forming the landing pad comprises the sub-steps of:
conformally depositing a blanket material; and
chemical mechanical polishing the blanket material.
12. The method of claim 1 , wherein the additional feature comprises a magnetic tunnel junction.
13. The method of claim 1 , wherein the anisotropic etching comprises ion beam etching.
14. The method of claim 1 , wherein the additional feature is patterned at least in part by a self-aligned double patterning process.
15. The method of claim 1 , wherein a maximum width of the additional feature is less than a maximum width of the landing pad and is less than a maximum width of the bottom contact.
16. A semiconductor device formed at least in part by the steps of:
forming a dielectric layer;
forming a bottom contact in the dielectric layer with an upper surface of the bottom contact exposed through an upper surface of the dielectric layer;
defining two sidewalls indented into the dielectric layer by recessing the bottom contact into the dielectric layer via selective etching, the two sidewalls bordering regions of the bottom contact removed during recessing;
forming two dielectric sidewall spacers along the two sidewalls;
forming a landing pad on the bottom contact between the two dielectric sidewall spacers, wherein the maximum width of the landing pad at the top surface of the landing pad is smaller than a width of the bottom contact at an interface between the landing pad and the bottom contact; and
forming an additional feature directly on top of the landing pad at least in part by anisotropic etching.
17. The semiconductor device of claim 16 , wherein the additional feature comprises a magnetic tunnel junction.
18. The of claim 16 , wherein a maximum width of the additional feature is less than a maximum width of the landing pad and is less than a maximum width of the bottom contact.