Semiconductor package
View Patent ↗Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.
1. A semiconductor package comprising:
a die comprising a first side and a second side opposing the first side, the second side coupled to a wafer backside coating;
a first end of a plurality of wires each bonded to the first side of the die;
a mold compound encapsulating the die and the plurality of wires, wherein the mold compound comprises a first side and a second side opposite the first side; and
a second end of the plurality of wires each exposed through the second side of the mold compound;
wherein a plurality of sidewalls of the mold compound are substantially perpendicular with the second side of the die.
2. The semiconductor package of claim 1 , wherein the wafer backside coating is a non-electrically conductive layer.
3. The semiconductor package of claim 1 , wherein the semiconductor package does not comprise a lead frame.
4. The semiconductor package of claim 1 , wherein five faces of the semiconductor package are entirely covered by the mold compound.
5. A semiconductor package comprising:
a die comprising a first side and a second side opposing the first side, the second side of the die coupled to a wafer backside coating;
a first end of a plurality of wires each bonded to the first side of the die;
a mold compound encapsulating the die and the plurality of wires, wherein the mold compound comprises a first side and a second side opposite the first side;
a second end of the plurality of wires each exposed through the second side of the mold compound; and
a plurality of electrical contacts bonded to the second end of the plurality of wires;
wherein the plurality of electrical contacts comprise one of a plurality of studs, a plurality of bumps, or a plurality of pads;
wherein a surface of the wafer backside coating is exposed through the second side of the mold compound; and
wherein a plurality of sidewalls of the mold compound are substantially perpendicular with the surface of the wafer backside coating exposed through the mold compound.
6. The semiconductor package of claim 5 , wherein the wafer backside coating is a non-electrically conductive layer.
7. The semiconductor package of claim 5 , wherein the semiconductor package does not comprise a lead frame.
8. The semiconductor package of claim 5 , wherein five faces of the semiconductor package are entirely covered by the mold compound.