Method for fabricating static random access memory having insulating layer with different thicknesses

1. A method for fabricating a semiconductor device, comprising:

providing a substrate having a first region and a second region, wherein the substrate comprises a semiconductor layer on top of an insulating layer;

forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate;

removing part of the insulating layer under the first front gate after forming the first front gate and the second front gate so that a thickness of the insulating layer directly under the first front gate is different from a thickness of the insulating layer directly under the second front gate;

forming a first back gate on the insulating layer under the first front gate; and

forming a second back gate under the second front gate.

2. The method of claim 1 , further comprising:

forming a first dielectric layer on the substrate to cover the first front gate and the second front gate; and

forming first contact plugs in the first dielectric layer to electrically connect the first front gate and the second front gate.

3. The method of claim 2 , further comprising:

forming a second dielectric layer on the insulating layer;

forming the first back gate adjacent to the second dielectric layer; and

forming the second back gate on the second dielectric layer.

4. The method of claim 3 , wherein bottom surfaces of the second dielectric layer and the first back gate are coplanar.

5. The method of claim 3 , further comprising forming a high-k dielectric layer on the second dielectric layer and the first back gate before forming the second back gate.

6. The method of claim 3 , further comprising forming the second back gate under the second front gate and a third back gate under the first back gate at the same time.

7. The method of claim 6 , wherein the first back gate and the third back gate are disposed within the first region under the first front gate.

8. The method of claim 6 , wherein the first back gate contacts the third back gate directly.

9. The method of claim 6 , further comprising:

forming a third dielectric layer on the insulating layer;

forming the second back gate and the third back gate in the third dielectric layer;

forming a second contact plug on the second back gate; and

forming a fourth back gate on the second contact plug.

10. The method of claim 9 , wherein the second back gate and the fourth back gate are disposed within the second region under the second front gate.