IP Library › Granted Patent US 11,469,368
Granted Patent B2
US 11,469,368 · App. 16/207,206 · Granted Oct 11, 2022

Semiconductor device and method for fabricating the same

Inventors: Ching-Wen Hung (Tainan, TW); Ya-Sheng Feng (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/02H01L21/76801H01L21/76838H01L43/12
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Quick Facts
Patent No.
US 11,469,368
App. No.
16/207,206
Granted
Oct 11, 2022
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Claims (15)

1. A semiconductor device, comprising:

a first inter-metal dielectric (IMD) layer on a substrate;

a metal interconnection in the first IMD layer;

a magnetic tunneling junction (MTJ) on the metal interconnection, wherein the MTJ comprises

a pinned layer on a bottom electrode layer;

a barrier layer on the pinned layer, wherein the barrier layer comprises a U-shape;

a free layer on the barrier layer; and

a top electrode layer on the free layer;

a spacer around the MTJ, wherein top surfaces of the barrier layer and the spacer are coplanar and a sidewall of the barrier layer is aligned with a sidewall of the pinned layer; and

a second IMD layer on the first IMD layer and around the spacer, wherein the top electrode layer contacts top surfaces of the barrier layer, the spacer, and the second IMD layer directly.

2. The semiconductor device of claim 1 , wherein top surfaces of the free layer, the barrier layer, the spacer, and the second IMD layer are coplanar.

3. The semiconductor device of claim 1 , wherein the barrier layer comprises:

a first vertical portion and a second vertical portion adjacent to two sides of the free layer; and

a horizontal portion connecting the first vertical portion and the second vertical portion.

4. The semiconductor device of claim 3 , wherein each of the first vertical portion and the second vertical portion are aligned with edges of the pinned layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2018
From: HUNG, CHING-WEN; FENG, YA-SHENG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 047648/0158 →
Priority Claims (1)
CN 201811286628.7 · Oct 31, 2018 · national
Continuity (1)
Related Publication 20200136015A1 · Apr 30, 2020