Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a substrate, a shallow trench isolation (STI) structure, a first source/drain, a second source/drain, and an isolation dielectric. The substrate has a semiconductor fin. The STI structure surrounds the semiconductor fin. The first source/drain is embedded in the semiconductor fin. The second source/drain is embedded in the semiconductor fin. The isolation dielectric is between the first and second source/drains and extending into the semiconductor fin. An upper surface of the STI structure is free from coverage of the isolation dielectric.
1. A semiconductor device, comprising:
a substrate having a semiconductor fin;
a shallow trench isolation (STI) structure surrounding the semiconductor fin;
a first source/drain embedded in the semiconductor fin;
a second source/drain embedded in the semiconductor fin; and
an isolation dielectric between the first and second source/drains and extending into the semiconductor fin, wherein an upper surface of the STI structure is free from coverage of the isolation dielectric.
2. The semiconductor device of claim 1 , wherein a bottom of the isolation dielectric is lower than a top surface of the STI structure.
3. The semiconductor device of claim 1 , wherein the isolation dielectric is in contact with the substrate.
4. The semiconductor device of claim 1 , wherein the isolation dielectric runs through the semiconductor fin from above the semiconductor fin to the substrate.
5. The semiconductor device of claim 1 , wherein the isolation dielectric is separated from the first and second source/drains.
6. The semiconductor device of claim 1 , wherein the substrate has a first portion under the isolation dielectric and a second portion adjacent to the isolation dielectric, and a top surface of the first portion is lower than a top surface of the second portion.
7. The semiconductor device of claim 1 , further comprising:
a first spacer over the semiconductor fin and in contact with the isolation dielectric.
8. The semiconductor device of claim 7 , further comprising:
a second spacer over the semiconductor fin, wherein the isolation dielectric is between the first and second spacers.
9. The semiconductor device of claim 1 , further comprising:
a gate stack over the semiconductor fin and having a top surface substantially level with a top surface of the isolation dielectric.
10. The semiconductor device of claim 1 , further comprising:
an insulating fin on the substrate, parallel to the semiconductor fin, and between the isolation dielectric and the semiconductor fin.
11. The semiconductor device of claim 1 , further comprising:
an insulating fin on the substrate and parallel to the semiconductor fin, wherein the isolation dielectric is in contact with a top surface of the insulating fin.
12. The semiconductor device of claim 1 , further comprising:
an insulating fin on the substrate and parallel to the semiconductor fin, wherein a bottom of the isolation dielectric is lower a bottom of the insulating fin.
13. A semiconductor device, comprising:
a substrate having a first semiconductor fin;
a shallow trench isolation (STI) structure surrounding the first semiconductor fin;
a first source/drain embedded in the first semiconductor fin;
a second source/drain embedded in the first semiconductor fin; and
an isolation dielectric between the first and second source/drains, extending into the first semiconductor fin, and in contact with a sidewall of the STI structure.
14. The semiconductor device of claim 13 , wherein a bottom of the isolation dielectric is lower than a top surface of the STI structure.
15. The semiconductor device of claim 13 , wherein a bottom of the isolation dielectric is lower than a bottom of the first semiconductor fin.
16. The semiconductor device of claim 13 , wherein the substrate further has a second semiconductor fin parallel to the first semiconductor fin and in contact with the isolation dielectric.
17. The semiconductor device of claim 13 , wherein the substrate further has a second semiconductor fin parallel to the first semiconductor fin, wherein the semiconductor device further comprises a gate stack straddling the second semiconductor fin and in contact with the isolation dielectric.
18. The semiconductor device of claim 17 , further comprising:
a hard mask over the gate stack and having a top surface substantially level with a top surface of the isolation dielectric.
19. A semiconductor device, comprising:
a substrate;
a semiconductor fin on the substrate;
an isolation structure surrounding the semiconductor fin;
a gate structure straddling the semiconductor fin;
a dielectric fin partially embedded in the isolation structure, projecting upwardly above the isolation structure, and in contact with a longitudinal end of the gate structure; and
a dielectric plug partially embedded in the substrate, landing on the dielectric fin, and in contact with the longitudinal end of the gate structure, wherein a bottommost portion of the dielectric plug is lower than a top surface of the substrate.
20. The semiconductor device of claim 19 , further comprising:
a hard mask layer over the gate structure, wherein the dielectric plug is in contact with a longitudinal end of the hard mask.