Image processing apparatus and non-transitory computer readable medium storing program to suppress deviation in sub-scanning direction at the time of image formation
An image processing apparatus includes a processing unit that shifts plural pieces of pixel data so as to suppress deviation in a sub-scanning direction at the time of image formation; a storage unit that stores the plural pieces of pixel data; and a converting unit that converts addresses of the plural pieces of pixel data such that a predetermined number of pieces of pixel data which are a unit of processing of the shift process are stored in a cache memory used by the storage unit at once.
1. An image processing apparatus comprising:
a memory; and
a processor, configured to:
shift a plurality of pieces of pixel data so as to suppress deviation in a sub-scanning direction at a time of image formation;
store the plurality of pieces of pixel data in the memory; and
convert addresses of the plurality of pieces of pixel data such that a predetermined number of pieces of pixel data which are a unit of processing of a shift process are stored in a cache memory used by the memory at once,
wherein in a case of issuing a write request of pixel data to be stored in the cache memory, a plurality of access requests corresponding to the predetermined number of pieces of pixel data are collected and issued consecutively,
wherein a block size is determined by a number of bytes per pixel, a minimum correction unit for the shift process, and a number of consecutive issuances of the plurality of access requests which are consecutively issued, and
wherein the number of consecutive issuances is set to satisfy a constraint condition that a data size determined by a maximum number of lines which is a processing range of the shift process and the block size is not more than a data storage size of the cache memory.
2. The image processing apparatus according to claim 1 ,
wherein in a process of writing the predetermined number of pieces of pixel data to the memory, storing data in the cache memory and sweeping out the data from the cache memory are not performed a plurality of times.
3. The image processing apparatus according to claim 1 ,
wherein the processor converts addresses of the plurality of pieces of pixel data such that the predetermined number of pieces of pixel data are included in a data string of consecutive addresses with a size which is not more than a data storage size of the cache memory.
4. The image processing apparatus according to claim 2 ,
wherein the processor converts addresses of the plurality of pieces of pixel data such that the predetermined number of pieces of pixel data are included in a data string of consecutive addresses with a size which is not more than a data storage size of the cache memory.
5. The image processing apparatus according to claim 3 ,
wherein the processor executes a process of rearranging the plurality of pieces of pixel data by converting addresses of the plurality of pieces of pixel data which are arranged in a matrix.
6. The image processing apparatus according to claim 4 ,
wherein the processor executes a process of rearranging the plurality of pieces of pixel data by converting addresses of the plurality of pieces of pixel data which are arranged in a matrix.
7. A non-transitory computer readable medium storing a program causing a processor of a computer to:
shift a plurality of pieces of pixel data so as to suppress deviation in a sub-scanning direction at a time of image formation; and
convert addresses of the plurality of pieces of pixel data such that a predetermined number of pieces of pixel data which is a unit of processing of a shift process is stored in a cache memory of a memory at once,
wherein in a case of issuing a write request of pixel data to be stored in the cache memory, a plurality of access requests corresponding to the predetermined number of pieces of pixel data are collected and issued consecutively,
wherein a block size is determined by a number of bytes per pixel, a minimum correction unit for the shift process, and a number of consecutive issuances of the plurality of access requests which are consecutively issued, and
wherein the number of consecutive issuances is set to satisfy a constraint condition that a data size determined by a maximum number of lines which is a processing range of the shift process and the block size is not more than a data storage size of the cache memory.
8. An image processing apparatus comprising:
processing means for shifting a plurality of pieces of pixel data so as to suppress deviation in a sub-scanning direction at a time of image formation;
storage means for storing the plurality of pieces of pixel data; and
converting means for converting addresses of the plurality of pieces of pixel data such that a predetermined number of pieces of pixel data which are a unit of processing of a shift process are stored in a cache memory used by the storage means at once,
wherein in a case of issuing a write request of pixel data to be stored in the cache memory, a plurality of access requests corresponding to the predetermined number of pieces of pixel data are collected and issued consecutively,
wherein a block size is determined by a number of bytes per pixel, a minimum correction unit for the shift process, and a number of consecutive issuances of the plurality of access requests which are consecutively issued, and
wherein the number of consecutive issuances is set to satisfy a constraint condition that a data size determined by a maximum number of lines which is a processing range of the shift process and the block size is not more than a data storage size of the cache memory.