IP Library Granted Patent US 11,061,846
Granted Patent B2
US 11,061,846 · App. 16/210,651 · Granted Jul 13, 2021

Secure crypto module including electrical shorting security layers

Inventors: Gerald K. Bartley (Rochester, MN); Darryl J. Becker (Rochester, MN); Matthew S. Doyle (Chatfield, MN); Joseph Kuczynski (North Port, FL); Timothy J. Tofil (Rochester, MN)
Assignee: International Business Machines Corporation
G06F13/4068G06F21/75G06F21/86G06F21/88G09C1/00H04L9/002H04L63/162
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Quick Facts
Patent No.
US 11,061,846
App. No.
16/210,651
Granted
Jul 13, 2021
Kind
B2
Abstract

A security matrix layer between a first and second conductive shorting layers are located within a printed circuit board (PCB). The security matrix layer includes at least two types of microcapsules with each type of microcapsule containing a different reactant. When the security matrix layer is accessed, drilled, or otherwise damaged, the microcapsules rupture and the reactants react to form at least an electrically conductive material. The electrically conductive material may contact and short the first and second conductive shorting layers.

Claims (17)

1. A method of securing a printed circuit board (PCB), the method comprising:

providing a security matrix layer between a first conductive layer of the PCB and a second conductive layer of the PCB, the security matrix layer comprising first microcapsules that include therein a first reactant and second microcapsules that include therein a second reactant different than the first reactant, wherein an electrically conductive material is formed by the first reactant chemically reacting with the second reactant;

detecting an electrical short of the first conductive layer and the second conductive layer by the electrically conductive material, the electrical short caused by an access void entirely through the first conductive layer, entirely through the security matrix layer, and at least partially through the second conductive layer, the access void rupturing one or more of the first microcapsules and rupturing one or more of the second microcapsules thereby forming the electrically conductive material upon a sidewall of the access void; and

programming, in response to detecting the electrical short, a security feature of the PCB to secure the PCB.

2. The method of claim 1 , wherein programming the security feature of the PCB disables functionality of the PCB.

3. The method of claim 1 , wherein programming the security feature of the PCB causes a fault in functionality of the PCB.

4. The method of claim 1 , wherein the PCB is a motherboard.

5. The method of claim 1 , wherein the PCB is an adapter card.

6. The method of claim 1 , wherein the PCB is a daughter card.

7. A method of securing a computer, the method comprising:

providing a security matrix layer between a first conductive layer of a printed circuit board (PCB) and a second conductive layer of the PCB, the security matrix layer comprising first microcapsules that include therein a first reactant and second microcapsules that include therein a second reactant different than the first reactant, wherein an electrically conductive material is formed by the first reactant chemically reacting with the second reactant;

detecting an electrical short of the first conductive layer and the second conductive layer by the electrically conductive material, the electrical short caused by an access void entirely through the first conductive layer, entirely through the security matrix layer, and at least partially through the second conductive layer, the access void rupturing one or more of the first microcapsules and rupturing one or more of the second microcapsules thereby forming the electrically conductive material upon a sidewall of the access void;

programming, in response to detecting the electrical short, a security feature of the PCB; and

erasing protected data stored within the computer, in response to the computer sensing that the security feature of the PCB has been programmed.

8. The method of claim 7 , wherein one or more subsequent functions of the computer are disabled, in response to the computer sensing that the security feature of the PCB has been programmed.

9. The method of claim 7 , wherein subsequent functionally of a processor of the computer is disabled, in response to the computer sensing that the security feature of the PCB has been programmed.

10. The method of claim 7 , wherein the protected data stored within the computer is erased from one or more hard drives of the computer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2018
From: BARTLEY, GERALD K.; BECKER, DARRYL J.; DOYLE, MATTHEW S.; KUCZYNSKI, JOSEPH; TOFIL, TIMOTHY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 047682/0448 →
Continuity (2)
Division 15048024 · Feb 19, 2016
Related Publication 20200125522A1 · Apr 23, 2020
Cited By (1)
US 12,431,939